#include "ctc_error.h"
#include "ctc_port.h"
#include "sys_usw_chip.h"
#include "drv_api.h"
#include "sys_usw_dmps.h"
#include "sys_usw_datapath.h"
#include "sys_at_datapath.h"
#include "sys_at_mac.h"
#include "sys_at_serdes.h"
#include "sys_usw_dmps_db.h"
#include "sys_usw_mac.h"

#include "sys_usw_qos_api.h"

#include "sys_usw_peri.h"

#include "sys_usw_wb_common.h"
#include "sys_usw_mcu.h"

#include "drv_api.h"
#include "usw/include/drv_chip_ctrl.h"
#include "usw/include/drv_common.h"
#include "sys_usw_register.h"
#include "sys_at_mcu.h"

///TODO: need delete
/*#include "ctc_vti.h"*/
#include "ctc_cli.h"
#include "ctc_cmd.h"
#undef g_ctc_vti
#define g_ctc_vti       (g_vty_client.ctc_vti)

extern uint32 g_port_link_mode;

extern int32 _sys_at_serdes_speed_switch_proc(uint8 lchip, uint16 serdes_id, uint8 serdes_speed);
extern int32 _sys_usw_dmps_db_dump(uint8 lchip, uint8 db_type, sal_file_t fp);
int32 _sys_at_serdes_lane_power_on_pre_cfg(uint8 lchip, uint16 serdes_id);
int32 _sys_at_serdes_lane_power_on_cfg(uint8 lchip, uint16 serdes_id, uint8 serdes_speed);
int32 _sys_at_serdes_lane_power_on_post_cfg(uint8 lchip, uint16 serdes_id, uint8 serdes_speed);
extern int32 _sys_at_serdes_power_on_per_hss(uint8 lchip, uint8 core_id, uint8 hss_id);
extern int32
_sys_at_mac_group_check_bw(uint8 lchip, uint8 core_id, uint8 mac_group_id, sys_dmps_ds_list_t* p_list);

#ifdef ARCTIC

sys_at_dmps_id_dictionary_t g_dmps_map_1pp[AT_SERDES_NUM_PER_CORE] = {
   /*pp_id  dp_id  txqm_id  sub_chan  mac_client  logic_serdes*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*0*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*1*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*2*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*3*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*4*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*5*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*6*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*7*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*8*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*9*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*10*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*11*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*12*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*13*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*14*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*15*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*16*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*17*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*18*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*19*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*20*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*21*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*22*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*23*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*24*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*25*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*26*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*27*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*28*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*29*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*30*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*31*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*32*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*33*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*34*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*35*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*36*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*37*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*38*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*39*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*40*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*41*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*42*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*43*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*44*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*45*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*46*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*47*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*48*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*49*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*50*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*51*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*52*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*53*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*54*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*55*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*56*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*57*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*58*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*59*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*60*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*61*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*62*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*63*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*64*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*65*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*66*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*67*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*68*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*69*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*70*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*71*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*72*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*73*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*74*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*75*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*76*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*77*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*78*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*79*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*80*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*81*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*82*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*83*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*84*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*85*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*86*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*87*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*88*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*89*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*90*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*91*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*92*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*93*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*94*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*95*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*96*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*97*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*98*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*99*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*100*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*101*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*102*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*103*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*104*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*105*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*106*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*107*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*108*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*109*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*110*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*111*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*112*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*113*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*114*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*115*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*116*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*117*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*118*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*119*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*120*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*121*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*122*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*123*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*124*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*125*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*126*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*127*/
    {3,     0,     0,       0,        0},         /*128*/
    {3,     0,     0,       1,        1},         /*129*/
    {3,     0,     0,       2,        2},         /*130*/
    {3,     0,     0,       3,        3},         /*131*/
    {3,     0,     0,       4,        4},         /*132*/
    {3,     0,     0,       5,        5},         /*133*/
    {3,     0,     0,       6,        6},         /*134*/
    {3,     0,     0,       7,        7},         /*135*/
    {3,     0,     1,       8,        16},        /*136*/
    {3,     0,     1,       9,        17},        /*137*/
    {3,     0,     1,       10,       18},        /*138*/
    {3,     0,     1,       11,       19},        /*139*/
    {3,     0,     1,       12,       20},        /*140*/
    {3,     0,     1,       13,       21},        /*141*/
    {3,     0,     1,       14,       22},        /*142*/
    {3,     0,     1,       15,       23},        /*143*/
    {3,     1,     0,       0,        0},         /*144*/
    {3,     1,     0,       1,        1},         /*145*/
    {3,     1,     0,       2,        2},         /*146*/
    {3,     1,     0,       3,        3},         /*147*/
    {3,     1,     0,       4,        4},         /*148*/
    {3,     1,     0,       5,        5},         /*149*/
    {3,     1,     0,       6,        6},         /*150*/
    {3,     1,     0,       7,        7},         /*151*/
    {3,     1,     1,       8,        16},        /*152*/
    {3,     1,     1,       9,        17},        /*153*/
    {3,     1,     1,       10,       18},        /*154*/
    {3,     1,     1,       11,       19},        /*155*/
    {3,     1,     1,       12,       20},        /*156*/
    {3,     1,     1,       13,       21},        /*157*/
    {3,     1,     1,       14,       22},        /*158*/
    {3,     1,     1,       15,       23},        /*159*/
};

const sys_at_dmps_id_dictionary_t g_dmps_map_ag[AT_SERDES_NUM_PER_CORE] = {
#ifdef PCS_ONLY
   /*pp_id  dp_id  txqm_id  sub_chan  mac_client  logic_serdes*/
    {0,     0,     0,       0,        0},         /*0*/
    {0,     0,     0,       1,        1},         /*1*/
    {0,     0,     0,       2,        2},         /*2*/
    {0,     0,     0,       3,        3},         /*3*/
    {0,     0,     0,       4,        4},         /*4*/
    {0,     0,     0,       5,        5},         /*5*/
    {0,     0,     0,       6,        6},         /*6*/
    {0,     0,     0,       7,        7},         /*7*/
    {0,     1,     0,       0,        0},         /*8*/
    {0,     1,     0,       1,        1},         /*9*/
    {0,     1,     0,       2,        2},         /*10*/
    {0,     1,     0,       3,        3},         /*11*/
    {0,     1,     0,       4,        4},         /*12*/
    {0,     1,     0,       5,        5},         /*13*/
    {0,     1,     0,       6,        6},         /*14*/
    {0,     1,     0,       7,        7},         /*15*/
    {1,     0,     0,       0,        0},         /*16*/
    {1,     0,     0,       1,        1},         /*17*/
    {1,     0,     0,       2,        2},         /*18*/
    {1,     0,     0,       3,        3},         /*19*/
    {1,     0,     0,       4,        4},         /*20*/
    {1,     0,     0,       5,        5},         /*21*/
    {1,     0,     0,       6,        6},         /*22*/
    {1,     0,     0,       7,        7},         /*23*/
    {1,     1,     0,       0,        0},         /*24*/
    {1,     1,     0,       1,        1},         /*25*/
    {1,     1,     0,       2,        2},         /*26*/
    {1,     1,     0,       3,        3},         /*27*/
    {1,     1,     0,       4,        4},         /*28*/
    {1,     1,     0,       5,        5},         /*29*/
    {1,     1,     0,       6,        6},         /*30*/
    {1,     1,     0,       7,        7},         /*31*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*32*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*33*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*34*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*35*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*36*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*37*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*38*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*39*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*40*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*41*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*42*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*43*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*44*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*45*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*46*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*47*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*48*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*49*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*50*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*51*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*52*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*53*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*54*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*55*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*56*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*57*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*58*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*59*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*60*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*61*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*62*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*63*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*64*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*65*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*66*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*67*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*68*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*69*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*70*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*71*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*72*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*73*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*74*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*75*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*76*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*77*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*78*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*79*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*80*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*81*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*82*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*83*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*84*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*85*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*86*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*87*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*88*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*89*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*90*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*91*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*92*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*93*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*94*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*95*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*96*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*97*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*98*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*99*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*100*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*101*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*102*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*103*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*104*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*105*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*106*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*107*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*108*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*109*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*110*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*111*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*112*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*113*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*114*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*115*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*116*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*117*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*118*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*119*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*120*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*121*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*122*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*123*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*124*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*125*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*126*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*127*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*128*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*129*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*130*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*131*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*132*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*133*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*134*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*135*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*136*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*137*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*138*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*139*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*140*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*141*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*142*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*143*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*144*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*145*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*146*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*147*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*148*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*149*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*150*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*151*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*152*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*153*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*154*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*155*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*156*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*157*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*158*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*159*/
#else
   /*pp_id  dp_id  txqm_id  sub_chan  mac_client  logic_serdes*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*0*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*1*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*2*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*3*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*4*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*5*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*6*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*7*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*8*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*9*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*10*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*11*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*12*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*13*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*14*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*15*/
    {0,     0,     0,       0,        0},         /*16*/
    {0,     0,     0,       1,        1},         /*17*/
    {0,     0,     0,       2,        2},         /*18*/
    {0,     0,     0,       3,        3},         /*19*/
    {0,     0,     0,       4,        4},         /*20*/
    {0,     0,     0,       5,        5},         /*21*/
    {0,     0,     0,       6,        6},         /*22*/
    {0,     0,     0,       7,        7},         /*23*/
    {0,     0,     1,       8,        16},        /*24*/
    {0,     0,     1,       9,        17},        /*25*/
    {0,     0,     1,       10,       18},        /*26*/
    {0,     0,     1,       11,       19},        /*27*/
    {0,     0,     1,       12,       20},        /*28*/
    {0,     0,     1,       13,       21},        /*29*/
    {0,     0,     1,       14,       22},        /*30*/
    {0,     0,     1,       15,       23},        /*31*/
    {1,     3,     0,       0,        96},        /*32*/
    {1,     3,     0,       1,        97},        /*33*/
    {1,     3,     0,       2,        98},        /*34*/
    {1,     3,     0,       3,        99},        /*35*/
    {1,     3,     0,       4,        100},       /*36*/
    {1,     3,     0,       5,        101},       /*37*/
    {1,     3,     0,       6,        102},       /*38*/
    {1,     3,     0,       7,        103},       /*39*/
    {0,     1,     0,       0,        32},        /*40*/
    {0,     1,     0,       1,        33},        /*41*/
    {0,     1,     0,       2,        34},        /*42*/
    {0,     1,     0,       3,        35},        /*43*/
    {0,     1,     0,       4,        36},        /*44*/
    {0,     1,     0,       5,        37},        /*45*/
    {0,     1,     0,       6,        38},        /*46*/
    {0,     1,     0,       7,        39},        /*47*/
    {1,     2,     0,       0,        64},        /*48*/
    {1,     2,     0,       1,        65},        /*49*/
    {1,     2,     0,       2,        66},        /*50*/
    {1,     2,     0,       3,        67},        /*51*/
    {1,     2,     0,       4,        68},        /*52*/
    {1,     2,     0,       5,        69},        /*53*/
    {1,     2,     0,       6,        70},        /*54*/
    {1,     2,     0,       7,        71},        /*55*/
    {2,     5,     1,       8,        176},       /*56*/
    {2,     5,     1,       9,        177},       /*57*/
    {2,     5,     1,       10,       178},       /*58*/
    {2,     5,     1,       11,       179},       /*59*/
    {2,     5,     1,       12,       180},       /*60*/
    {2,     5,     1,       13,       181},       /*61*/
    {2,     5,     1,       14,       182},       /*62*/
    {2,     5,     1,       15,       183},       /*63*/
    {0,     1,     1,       8,        48},        /*64*/
    {0,     1,     1,       9,        49},        /*65*/
    {0,     1,     1,       10,       50},        /*66*/
    {0,     1,     1,       11,       51},        /*67*/
    {0,     1,     1,       12,       52},        /*68*/
    {0,     1,     1,       13,       53},        /*69*/
    {0,     1,     1,       14,       54},        /*70*/
    {0,     1,     1,       15,       55},        /*71*/
    {1,     2,     1,       8,        80},        /*72*/
    {1,     2,     1,       9,        81},        /*73*/
    {1,     2,     1,       10,       82},        /*74*/
    {1,     2,     1,       11,       83},        /*75*/
    {1,     2,     1,       12,       84},        /*76*/
    {1,     2,     1,       13,       85},        /*77*/
    {1,     2,     1,       14,       86},        /*78*/
    {1,     2,     1,       15,       87},        /*79*/
    {2,     4,     1,       8,        144},       /*80*/
    {2,     4,     1,       9,        145},       /*81*/
    {2,     4,     1,       10,       146},       /*82*/
    {2,     4,     1,       11,       147},       /*83*/
    {2,     4,     1,       12,       148},       /*84*/
    {2,     4,     1,       13,       149},       /*85*/
    {2,     4,     1,       14,       150},       /*86*/
    {2,     4,     1,       15,       151},       /*87*/
    {3,     7,     1,       8,        240},       /*88*/
    {3,     7,     1,       9,        241},       /*89*/
    {3,     7,     1,       10,       242},       /*90*/
    {3,     7,     1,       11,       243},       /*91*/
    {3,     7,     1,       12,       244},       /*92*/
    {3,     7,     1,       13,       245},       /*93*/
    {3,     7,     1,       14,       246},       /*94*/
    {3,     7,     1,       15,       247},       /*95*/
    {1,     3,     1,       8,        112},       /*96*/
    {1,     3,     1,       9,        113},       /*97*/
    {1,     3,     1,       10,       114},       /*98*/
    {1,     3,     1,       11,       115},       /*99*/
    {1,     3,     1,       12,       116},       /*100*/
    {1,     3,     1,       13,       117},       /*101*/
    {1,     3,     1,       14,       118},       /*102*/
    {1,     3,     1,       15,       119},       /*103*/
    {2,     4,     0,       0,        128},       /*104*/
    {2,     4,     0,       1,        129},       /*105*/
    {2,     4,     0,       2,        130},       /*106*/
    {2,     4,     0,       3,        131},       /*107*/
    {2,     4,     0,       4,        132},       /*108*/
    {2,     4,     0,       5,        133},       /*109*/
    {2,     4,     0,       6,        134},       /*110*/
    {2,     4,     0,       7,        135},       /*111*/
    {3,     7,     0,       0,        224},       /*112*/
    {3,     7,     0,       1,        225},       /*113*/
    {3,     7,     0,       2,        226},       /*114*/
    {3,     7,     0,       3,        227},       /*115*/
    {3,     7,     0,       4,        228},       /*116*/
    {3,     7,     0,       5,        229},       /*117*/
    {3,     7,     0,       6,        230},       /*118*/
    {3,     7,     0,       7,        231},       /*119*/
    {2,     5,     0,       0,        160},       /*120*/
    {2,     5,     0,       1,        161},       /*121*/
    {2,     5,     0,       2,        162},       /*122*/
    {2,     5,     0,       3,        163},       /*123*/
    {2,     5,     0,       4,        164},       /*124*/
    {2,     5,     0,       5,        165},       /*125*/
    {2,     5,     0,       6,        166},       /*126*/
    {2,     5,     0,       7,        167},       /*127*/
    {3,     6,     1,       8,        208},       /*128*/
    {3,     6,     1,       9,        209},       /*129*/
    {3,     6,     1,       10,       210},       /*130*/
    {3,     6,     1,       11,       211},       /*131*/
    {3,     6,     1,       12,       212},       /*132*/
    {3,     6,     1,       13,       213},       /*133*/
    {3,     6,     1,       14,       214},       /*134*/
    {3,     6,     1,       15,       215},       /*135*/
    {3,     6,     0,       0,        192},       /*136*/
    {3,     6,     0,       1,        193},       /*137*/
    {3,     6,     0,       2,        194},       /*138*/
    {3,     6,     0,       3,        195},       /*139*/
    {3,     6,     0,       4,        196},       /*140*/
    {3,     6,     0,       5,        197},       /*141*/
    {3,     6,     0,       6,        198},       /*142*/
    {3,     6,     0,       7,        199},       /*143*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*144*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*145*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*146*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*147*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*148*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*149*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*150*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*151*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*152*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*153*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*154*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*155*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*156*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*157*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*158*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*159*/
#endif
};

const sys_at_dmps_id_dictionary_t g_dmps_map_ag_full[AT_SERDES_NUM_PER_CORE] = {
    /*pp_id  dp_id  txqm_id  sub_chan  mac_client  logic_serdes*/
     {0,     0,     0,       0,        0},         /*0*/
     {0,     0,     0,       1,        1},         /*1*/
     {0,     0,     0,       2,        2},         /*2*/
     {0,     0,     0,       3,        3},         /*3*/
     {0,     0,     0,       4,        4},         /*4*/
     {0,     0,     0,       5,        5},         /*5*/
     {0,     0,     0,       6,        6},         /*6*/
     {0,     0,     0,       7,        7},         /*7*/
     {0,     0,     1,       16,       16},        /*8*/
     {0,     0,     1,       17,       17},        /*9*/
     {0,     0,     1,       18,       18},        /*10*/
     {0,     0,     1,       19,       19},        /*11*/
     {0,     0,     1,       20,       20},        /*12*/
     {0,     0,     1,       21,       21},        /*13*/
     {0,     0,     1,       22,       22},        /*14*/
     {0,     0,     1,       23,       23},        /*15*/
     {0,     0,     0,       8,        8},         /*16*/
     {0,     0,     0,       9,        9},         /*17*/
     {0,     0,     0,       10,       10},        /*18*/
     {0,     0,     0,       11,       11},        /*19*/
     {0,     0,     0,       12,       12},        /*20*/
     {0,     0,     0,       13,       13},        /*21*/
     {0,     0,     0,       14,       14},        /*22*/
     {0,     0,     0,       15,       15},        /*23*/
     {1,     2,     1,       8,        80},        /*24*/
     {1,     2,     1,       9,        81},        /*25*/
     {1,     2,     1,       10,       82},        /*26*/
     {1,     2,     1,       11,       83},        /*27*/
     {1,     2,     1,       12,       84},        /*28*/
     {1,     2,     1,       13,       85},        /*29*/
     {1,     2,     1,       14,       86},        /*30*/
     {1,     2,     1,       15,       87},        /*31*/
     {0,     1,     0,       0,        32},        /*32*/
     {0,     1,     0,       1,        33},        /*33*/
     {0,     1,     0,       2,        34},        /*34*/
     {0,     1,     0,       3,        35},        /*35*/
     {0,     1,     0,       4,        36},        /*36*/
     {0,     1,     0,       5,        37},        /*37*/
     {0,     1,     0,       6,        38},        /*38*/
     {0,     1,     0,       7,        39},        /*39*/
     {0,     1,     0,       8,        40},        /*40*/
     {0,     1,     0,       9,        41},        /*41*/
     {0,     1,     0,       10,       42},        /*42*/
     {0,     1,     0,       11,       43},        /*43*/
     {0,     1,     0,       12,       44},        /*44*/
     {0,     1,     0,       13,       45},        /*45*/
     {0,     1,     0,       14,       46},        /*46*/
     {0,     1,     0,       15,       47},        /*47*/
     {1,     2,     0,       0,        64},        /*48*/
     {1,     2,     0,       1,        65},        /*49*/
     {1,     2,     0,       2,        66},        /*50*/
     {1,     2,     0,       3,        67},        /*51*/
     {1,     2,     0,       4,        68},        /*52*/
     {1,     2,     0,       5,        69},        /*53*/
     {1,     2,     0,       6,        70},        /*54*/
     {1,     2,     0,       7,        71},        /*55*/
     {2,     5,     1,       16,       176},       /*56*/
     {2,     5,     1,       17,       177},       /*57*/
     {2,     5,     1,       18,       178},       /*58*/
     {2,     5,     1,       19,       179},       /*59*/
     {2,     5,     1,       20,       180},       /*60*/
     {2,     5,     1,       21,       181},       /*61*/
     {2,     5,     1,       22,       182},       /*62*/
     {2,     5,     1,       23,       183},       /*63*/
     {0,     1,     1,       16,       48},        /*64*/
     {0,     1,     1,       17,       49},        /*65*/
     {0,     1,     1,       18,       50},        /*66*/
     {0,     1,     1,       19,       51},        /*67*/
     {0,     1,     1,       20,       52},        /*68*/
     {0,     1,     1,       21,       53},        /*69*/
     {0,     1,     1,       22,       54},        /*70*/
     {0,     1,     1,       23,       55},        /*71*/
     {2,     5,     0,       0,        160},       /*72*/
     {2,     5,     0,       1,        161},       /*73*/
     {2,     5,     0,       2,        162},       /*74*/
     {2,     5,     0,       3,        163},       /*75*/
     {2,     5,     0,       4,        164},       /*76*/
     {2,     5,     0,       5,        165},       /*77*/
     {2,     5,     0,       6,        166},       /*78*/
     {2,     5,     0,       7,        167},       /*79*/
     {1,     3,     0,       0,        96},        /*80*/
     {1,     3,     0,       1,        97},        /*81*/
     {1,     3,     0,       2,        98},        /*82*/
     {1,     3,     0,       3,        99},        /*83*/
     {1,     3,     0,       4,        100},       /*84*/
     {1,     3,     0,       5,        101},       /*85*/
     {1,     3,     0,       6,        102},       /*86*/
     {1,     3,     0,       7,        103},       /*87*/
     {3,     7,     1,       16,       240},       /*88*/
     {3,     7,     1,       17,       241},       /*89*/
     {3,     7,     1,       18,       242},       /*90*/
     {3,     7,     1,       19,       243},       /*91*/
     {3,     7,     1,       20,       244},       /*92*/
     {3,     7,     1,       21,       245},       /*93*/
     {3,     7,     1,       22,       246},       /*94*/
     {3,     7,     1,       23,       247},       /*95*/
     {1,     3,     1,       8,        112},       /*96*/
     {1,     3,     1,       9,        113},       /*97*/
     {1,     3,     1,       10,       114},       /*98*/
     {1,     3,     1,       11,       115},       /*99*/
     {1,     3,     1,       12,       116},       /*100*/
     {1,     3,     1,       13,       117},       /*101*/
     {1,     3,     1,       14,       118},       /*102*/
     {1,     3,     1,       15,       119},       /*103*/
     {2,     4,     0,       0,        128},       /*104*/
     {2,     4,     0,       1,        129},       /*105*/
     {2,     4,     0,       2,        130},       /*106*/
     {2,     4,     0,       3,        131},       /*107*/
     {2,     4,     0,       4,        132},       /*108*/
     {2,     4,     0,       5,        133},       /*109*/
     {2,     4,     0,       6,        134},       /*110*/
     {2,     4,     0,       7,        135},       /*111*/
     {3,     7,     0,       8,        232},       /*112*/
     {3,     7,     0,       9,        233},       /*113*/
     {3,     7,     0,       10,       234},       /*114*/
     {3,     7,     0,       11,       235},       /*115*/
     {3,     7,     0,       12,       236},       /*116*/
     {3,     7,     0,       13,       237},       /*117*/
     {3,     7,     0,       14,       238},       /*118*/
     {3,     7,     0,       15,       239},       /*119*/
     {3,     7,     0,       0,        224},       /*120*/
     {3,     7,     0,       1,        225},       /*121*/
     {3,     7,     0,       2,        226},       /*122*/
     {3,     7,     0,       3,        227},       /*123*/
     {3,     7,     0,       4,        228},       /*124*/
     {3,     7,     0,       5,        229},       /*125*/
     {3,     7,     0,       6,        230},       /*126*/
     {3,     7,     0,       7,        231},       /*127*/
     {2,     4,     1,       16,       144},       /*128*/
     {2,     4,     1,       17,       145},       /*129*/
     {2,     4,     1,       18,       146},       /*130*/
     {2,     4,     1,       19,       147},       /*131*/
     {2,     4,     1,       20,       148},       /*132*/
     {2,     4,     1,       21,       149},       /*133*/
     {2,     4,     1,       22,       150},       /*134*/
     {2,     4,     1,       23,       151},       /*135*/
     {3,     6,     0,       8,        200},       /*136*/
     {3,     6,     0,       9,        201},       /*137*/
     {3,     6,     0,       10,       202},       /*138*/
     {3,     6,     0,       11,       203},       /*139*/
     {3,     6,     0,       12,       204},       /*140*/
     {3,     6,     0,       13,       205},       /*141*/
     {3,     6,     0,       14,       206},       /*142*/
     {3,     6,     0,       15,       207},       /*143*/
     {3,     6,     1,       16,       208},       /*144*/
     {3,     6,     1,       17,       209},       /*145*/
     {3,     6,     1,       18,       210},       /*146*/
     {3,     6,     1,       19,       211},       /*147*/
     {3,     6,     1,       20,       212},       /*148*/
     {3,     6,     1,       21,       213},       /*149*/
     {3,     6,     1,       22,       214},       /*150*/
     {3,     6,     1,       23,       215},       /*151*/
     {3,     6,     0,       0,        192},       /*152*/
     {3,     6,     0,       1,        193},       /*153*/
     {3,     6,     0,       2,        194},       /*154*/
     {3,     6,     0,       3,        195},       /*155*/
     {3,     6,     0,       4,        196},       /*156*/
     {3,     6,     0,       5,        197},       /*157*/
     {3,     6,     0,       6,        198},       /*158*/
     {3,     6,     0,       7,        199},       /*159*/
};

const sys_at_dmps_id_dictionary_t g_dmps_map_ag_full_high[AT_SERDES_NUM_PER_CORE] = {
    /*pp_id  dp_id  txqm_id  sub_chan  mac_client  logic_serdes*/
     {0,     0,     0,       0,        0},         /*0*/
     {0,     0,     0,       1,        1},         /*1*/
     {0,     0,     0,       2,        2},         /*2*/
     {0,     0,     0,       3,        3},         /*3*/
     {0,     0,     0,       4,        4},         /*4*/
     {0,     0,     0,       5,        5},         /*5*/
     {0,     0,     0,       6,        6},         /*6*/
     {0,     0,     0,       7,        7},         /*7*/
     {1,     2,     1,       8 ,       80},        /*8*/
     {1,     2,     1,       9 ,       81},        /*9*/
     {1,     2,     1,       10,       82},        /*10*/
     {1,     2,     1,       11,       83},        /*11*/
     {1,     2,     1,       12,       84},        /*12*/
     {1,     2,     1,       13,       85},        /*13*/
     {1,     2,     1,       14,       86},        /*14*/
     {1,     2,     1,       15,       87},        /*15*/
     {0,     0,     0,       8,        8},         /*16*/
     {0,     0,     0,       9,        9},         /*17*/
     {0,     0,     0,       10,       10},        /*18*/
     {0,     0,     0,       11,       11},        /*19*/
     {0,     0,     0,       12,       12},        /*20*/
     {0,     0,     0,       13,       13},        /*21*/
     {0,     0,     0,       14,       14},        /*22*/
     {0,     0,     0,       15,       15},        /*23*/
     {0,     0,     1,       16,       16},        /*24*/
     {0,     0,     1,       17,       17},        /*25*/
     {0,     0,     1,       18,       18},        /*26*/
     {0,     0,     1,       19,       19},        /*27*/
     {0,     0,     1,       20,       20},        /*28*/
     {0,     0,     1,       21,       21},        /*29*/
     {0,     0,     1,       22,       22},        /*30*/
     {0,     0,     1,       23,       23},        /*31*/
     {1,     3,     0,       0,        96 },       /*32*/
     {1,     3,     0,       1,        97 },       /*33*/
     {1,     3,     0,       2,        98 },       /*34*/
     {1,     3,     0,       3,        99 },       /*35*/
     {1,     3,     0,       4,        100},       /*36*/
     {1,     3,     0,       5,        101},       /*37*/
     {1,     3,     0,       6,        102},       /*38*/
     {1,     3,     0,       7,        103},       /*39*/
     {0,     1,     0,       8,        32},        /*40*/
     {0,     1,     0,       9,        33},        /*41*/
     {0,     1,     0,       10,       34},        /*42*/
     {0,     1,     0,       11,       35},        /*43*/
     {0,     1,     0,       12,       36},        /*44*/
     {0,     1,     0,       13,       37},        /*45*/
     {0,     1,     0,       14,       38},        /*46*/
     {0,     1,     0,       15,       39},        /*47*/
     {1,     2,     0,       0,        64},        /*48*/
     {1,     2,     0,       1,        65},        /*49*/
     {1,     2,     0,       2,        66},        /*50*/
     {1,     2,     0,       3,        67},        /*51*/
     {1,     2,     0,       4,        68},        /*52*/
     {1,     2,     0,       5,        69},        /*53*/
     {1,     2,     0,       6,        70},        /*54*/
     {1,     2,     0,       7,        71},        /*55*/
     {2,     5,     1,       16,       176},       /*56*/
     {2,     5,     1,       17,       177},       /*57*/
     {2,     5,     1,       18,       178},       /*58*/
     {2,     5,     1,       19,       179},       /*59*/
     {2,     5,     1,       20,       180},       /*60*/
     {2,     5,     1,       21,       181},       /*61*/
     {2,     5,     1,       22,       182},       /*62*/
     {2,     5,     1,       23,       183},       /*63*/
     {0,     1,     1,       16,       48},        /*64*/
     {0,     1,     1,       17,       49},        /*65*/
     {0,     1,     1,       18,       50},        /*66*/
     {0,     1,     1,       19,       51},        /*67*/
     {0,     1,     1,       20,       52},        /*68*/
     {0,     1,     1,       21,       53},        /*69*/
     {0,     1,     1,       22,       54},        /*70*/
     {0,     1,     1,       23,       55},        /*71*/
     {1,     2,     1,       16,       88},        /*72*/
     {1,     2,     1,       17,       89},        /*73*/
     {1,     2,     1,       18,       90},        /*74*/
     {1,     2,     1,       19,       91},        /*75*/
     {1,     2,     1,       20,       92},        /*76*/
     {1,     2,     1,       21,       93},        /*77*/
     {1,     2,     1,       22,       94},        /*78*/
     {1,     2,     1,       23,       95},        /*79*/
     {2,     4,     1,       16,       152},       /*80*/
     {2,     4,     1,       17,       153},       /*81*/
     {2,     4,     1,       18,       154},       /*82*/
     {2,     4,     1,       19,       155},       /*83*/
     {2,     4,     1,       20,       156},       /*84*/
     {2,     4,     1,       21,       157},       /*85*/
     {2,     4,     1,       22,       158},       /*86*/
     {2,     4,     1,       23,       159},       /*87*/
     {3,     7,     1,       16,       240},       /*88*/
     {3,     7,     1,       17,       241},       /*89*/
     {3,     7,     1,       18,       242},       /*90*/
     {3,     7,     1,       19,       243},       /*91*/
     {3,     7,     1,       20,       244},       /*92*/
     {3,     7,     1,       21,       245},       /*93*/
     {3,     7,     1,       22,       246},       /*94*/
     {3,     7,     1,       23,       247},       /*95*/
     {1,     3,     1,       8,        112},       /*96*/
     {1,     3,     1,       9,        113},       /*97*/
     {1,     3,     1,       10,       114},       /*98*/
     {1,     3,     1,       11,       115},       /*99*/
     {1,     3,     1,       12,       116},       /*100*/
     {1,     3,     1,       13,       117},       /*101*/
     {1,     3,     1,       14,       118},       /*102*/
     {1,     3,     1,       15,       119},       /*103*/
     {2,     4,     0,       0,        128},       /*104*/
     {2,     4,     0,       1,        129},       /*105*/
     {2,     4,     0,       2,        130},       /*106*/
     {2,     4,     0,       3,        131},       /*107*/
     {2,     4,     0,       4,        132},       /*108*/
     {2,     4,     0,       5,        133},       /*109*/
     {2,     4,     0,       6,        134},       /*110*/
     {2,     4,     0,       7,        135},       /*111*/
     {3,     7,     0,       0,        224},       /*112*/
     {3,     7,     0,       1,        225},       /*113*/
     {3,     7,     0,       2,        226},       /*114*/
     {3,     7,     0,       3,        227},       /*115*/
     {3,     7,     0,       4,        228},       /*116*/
     {3,     7,     0,       5,        229},       /*117*/
     {3,     7,     0,       6,        230},       /*118*/
     {3,     7,     0,       7,        231},       /*119*/
     {2,     5,     0,       0,        160},       /*120*/
     {2,     5,     0,       1,        161},       /*121*/
     {2,     5,     0,       2,        162},       /*122*/
     {2,     5,     0,       3,        163},       /*123*/
     {2,     5,     0,       4,        164},       /*124*/
     {2,     5,     0,       5,        165},       /*125*/
     {2,     5,     0,       6,        166},       /*126*/
     {2,     5,     0,       7,        167},       /*127*/
     {3,     6,     1,       16,       208},       /*128*/
     {3,     6,     1,       17,       209},       /*129*/
     {3,     6,     1,       18,       210},       /*130*/
     {3,     6,     1,       19,       211},       /*131*/
     {3,     6,     1,       20,       212},       /*132*/
     {3,     6,     1,       21,       213},       /*133*/
     {3,     6,     1,       22,       214},       /*134*/
     {3,     6,     1,       23,       215},       /*135*/
     {3,     6,     0,       8,        200},       /*136*/
     {3,     6,     0,       9,        201},       /*137*/
     {3,     6,     0,       10,       202},       /*138*/
     {3,     6,     0,       11,       203},       /*139*/
     {3,     6,     0,       12,       204},       /*140*/
     {3,     6,     0,       13,       205},       /*141*/
     {3,     6,     0,       14,       206},       /*142*/
     {3,     6,     0,       15,       207},       /*143*/
     {2,     4,     1,       8 ,       144},       /*144*/
     {2,     4,     1,       9 ,       145},       /*145*/
     {2,     4,     1,       10,       146},       /*146*/
     {2,     4,     1,       11,       147},       /*147*/
     {2,     4,     1,       12,       148},       /*148*/
     {2,     4,     1,       13,       149},       /*149*/
     {2,     4,     1,       14,       150},       /*150*/
     {2,     4,     1,       15,       151},       /*151*/
     {3,     6,     0,       0,        192},       /*152*/
     {3,     6,     0,       1,        193},       /*153*/
     {3,     6,     0,       2,        194},       /*154*/
     {3,     6,     0,       3,        195},       /*155*/
     {3,     6,     0,       4,        196},       /*156*/
     {3,     6,     0,       5,        197},       /*157*/
     {3,     6,     0,       6,        198},       /*158*/
     {3,     6,     0,       7,        199},       /*159*/
};


const sys_at_dmps_id_dictionary_t g_dmps_map_pg[AT_SERDES_NUM_PER_CORE] = {
   /*pp_id  dp_id  txqm_id  sub_chan  mac_client  logic_serdes*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*0*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*1*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*2*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*3*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*4*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*5*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*6*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*7*/
    {0,     0,     1,       8,        16},        /*8*/
    {0,     0,     1,       9,        17},        /*9*/
    {0,     0,     1,       10,       18},        /*10*/
    {0,     0,     1,       11,       19},        /*11*/
    {0,     0,     1,       12,       20},        /*12*/
    {0,     0,     1,       13,       21},        /*13*/
    {0,     0,     1,       14,       22},        /*14*/
    {0,     0,     1,       15,       23},        /*15*/
    {0,     0,     0,       0,        0},         /*16*/
    {0,     0,     0,       1,        1},         /*17*/
    {0,     0,     0,       2,        2},         /*18*/
    {0,     0,     0,       3,        3},         /*19*/
    {0,     0,     0,       4,        4},         /*20*/
    {0,     0,     0,       5,        5},         /*21*/
    {0,     0,     0,       6,        6},         /*22*/
    {0,     0,     0,       7,        7},         /*23*/
    {0,     0,     1,       16,       24},        /*24*/
    {0,     0,     1,       17,       25},        /*25*/
    {0,     0,     1,       18,       26},        /*26*/
    {0,     0,     1,       19,       27},        /*27*/
    {0,     0,     1,       20,       28},        /*28*/
    {0,     0,     1,       21,       29},        /*29*/
    {0,     0,     1,       22,       30},        /*30*/
    {0,     0,     1,       23,       31},        /*31*/
    {0,     1,     0,       0,        32},        /*32*/
    {0,     1,     0,       1,        33},        /*33*/
    {0,     1,     0,       2,        34},        /*34*/
    {0,     1,     0,       3,        35},        /*35*/
    {0,     1,     0,       4,        36},        /*36*/
    {0,     1,     0,       5,        37},        /*37*/
    {0,     1,     0,       6,        38},        /*38*/
    {0,     1,     0,       7,        39},        /*39*/
    {0,     1,     0,       8,        40},        /*40*/
    {0,     1,     0,       9,        41},        /*41*/
    {0,     1,     0,       10,       42},        /*42*/
    {0,     1,     0,       11,       43},        /*43*/
    {0,     1,     0,       12,       44},        /*44*/
    {0,     1,     0,       13,       45},        /*45*/
    {0,     1,     0,       14,       46},        /*46*/
    {0,     1,     0,       15,       47},        /*47*/
    {1,     2,     0,       0,        64},        /*48*/
    {1,     2,     0,       1,        65},        /*49*/
    {1,     2,     0,       2,        66},        /*50*/
    {1,     2,     0,       3,        67},        /*51*/
    {1,     2,     0,       4,        68},        /*52*/
    {1,     2,     0,       5,        69},        /*53*/
    {1,     2,     0,       6,        70},        /*54*/
    {1,     2,     0,       7,        71},        /*55*/
    {1,     2,     0,       8,        72},        /*56*/
    {1,     2,     0,       9,        73},        /*57*/
    {1,     2,     0,       10,       74},        /*58*/
    {1,     2,     0,       11,       75},        /*59*/
    {1,     2,     0,       12,       76},        /*60*/
    {1,     2,     0,       13,       77},        /*61*/
    {1,     2,     0,       14,       78},        /*62*/
    {1,     2,     0,       15,       79},        /*63*/
    {0,     1,     1,       16,       48},        /*64*/
    {0,     1,     1,       17,       49},        /*65*/
    {0,     1,     1,       18,       50},        /*66*/
    {0,     1,     1,       19,       51},        /*67*/
    {0,     1,     1,       20,       52},        /*68*/
    {0,     1,     1,       21,       53},        /*69*/
    {0,     1,     1,       22,       54},        /*70*/
    {0,     1,     1,       23,       55},        /*71*/
    {1,     2,     1,       16,       80},        /*72*/
    {1,     2,     1,       17,       81},        /*73*/
    {1,     2,     1,       18,       82},        /*74*/
    {1,     2,     1,       19,       83},        /*75*/
    {1,     2,     1,       20,       84},        /*76*/
    {1,     2,     1,       21,       85},        /*77*/
    {1,     2,     1,       22,       86},        /*78*/
    {1,     2,     1,       23,       87},        /*79*/
    {1,     3,     0,       0,        96},        /*80*/
    {1,     3,     0,       1,        97},        /*81*/
    {1,     3,     0,       2,        98},        /*82*/
    {1,     3,     0,       3,        99},        /*83*/
    {1,     3,     0,       4,        100},       /*84*/
    {1,     3,     0,       5,        101},       /*85*/
    {1,     3,     0,       6,        102},       /*86*/
    {1,     3,     0,       7,        103},       /*87*/
    {2,     5,     1,       16,       176},       /*88*/
    {2,     5,     1,       17,       177},       /*89*/
    {2,     5,     1,       18,       178},       /*90*/
    {2,     5,     1,       19,       179},       /*91*/
    {2,     5,     1,       20,       180},       /*92*/
    {2,     5,     1,       21,       181},       /*93*/
    {2,     5,     1,       22,       182},       /*94*/
    {2,     5,     1,       23,       183},       /*95*/
    {1,     3,     1,       16,       120},       /*96*/
    {1,     3,     1,       17,       121},       /*97*/
    {1,     3,     1,       18,       122},       /*98*/
    {1,     3,     1,       19,       123},       /*99*/
    {1,     3,     1,       20,       124},       /*100*/
    {1,     3,     1,       21,       125},       /*101*/
    {1,     3,     1,       22,       126},       /*102*/
    {1,     3,     1,       23,       127},       /*103*/
    {1,     3,     1,       8,        112},       /*104*/
    {1,     3,     1,       9,        113},       /*105*/
    {1,     3,     1,       10,       114},       /*106*/
    {1,     3,     1,       11,       115},       /*107*/
    {1,     3,     1,       12,       116},       /*108*/
    {1,     3,     1,       13,       117},       /*109*/
    {1,     3,     1,       14,       118},       /*110*/
    {1,     3,     1,       15,       119},       /*111*/
    {2,     5,     0,       8,        168},       /*112*/
    {2,     5,     0,       9,        169},       /*113*/
    {2,     5,     0,       10,       170},       /*114*/
    {2,     5,     0,       11,       171},       /*115*/
    {2,     5,     0,       12,       172},       /*116*/
    {2,     5,     0,       13,       173},       /*117*/
    {2,     5,     0,       14,       174},       /*118*/
    {2,     5,     0,       15,       175},       /*119*/
    {2,     5,     0,       0,        160},       /*120*/
    {2,     5,     0,       1,        161},       /*121*/
    {2,     5,     0,       2,        162},       /*122*/
    {2,     5,     0,       3,        163},       /*123*/
    {2,     5,     0,       4,        164},       /*124*/
    {2,     5,     0,       5,        165},       /*125*/
    {2,     5,     0,       6,        166},       /*126*/
    {2,     5,     0,       7,        167},       /*127*/
    {2,     4,     1,       16,       152},       /*128*/
    {2,     4,     1,       17,       153},       /*129*/
    {2,     4,     1,       18,       154},       /*130*/
    {2,     4,     1,       19,       155},       /*131*/
    {2,     4,     1,       20,       156},       /*132*/
    {2,     4,     1,       21,       157},       /*133*/
    {2,     4,     1,       22,       158},       /*134*/
    {2,     4,     1,       23,       159},       /*135*/
    {2,     4,     0,       0,        128},       /*136*/
    {2,     4,     0,       1,        129},       /*137*/
    {2,     4,     0,       2,        130},       /*138*/
    {2,     4,     0,       3,        131},       /*139*/
    {2,     4,     0,       4,        132},       /*140*/
    {2,     4,     0,       5,        133},       /*141*/
    {2,     4,     0,       6,        134},       /*142*/
    {2,     4,     0,       7,        135},       /*143*/
    {2,     4,     1,       8,        144},       /*144*/
    {2,     4,     1,       9,        145},       /*145*/
    {2,     4,     1,       10,       146},       /*146*/
    {2,     4,     1,       11,       147},       /*147*/
    {2,     4,     1,       12,       148},       /*148*/
    {2,     4,     1,       13,       149},       /*149*/
    {2,     4,     1,       14,       150},       /*150*/
    {2,     4,     1,       15,       151},       /*151*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*152*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*153*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*154*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*155*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*156*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*157*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*158*/
    {0xff,  0xff,  0xff,    0xff,     0xffff},    /*159*/
};

extern sal_file_t g_tm_dump_fp;
extern uint8 g_dmps_dbg_sw;
extern uint8 g_at_hata_en;

extern int32
_sys_at_mac_set_nw_config_by_mac_id(uint8 lchip, uint16 logic_serdes);
extern int32
_sys_at_mac_get_cal_by_lane(uint8 lchip, uint8 idx, uint8 speed_mode, uint8* cal_value);
extern int32
_sys_at_mac_set_mcmac_stats_init_reg(uint8 lchip, uint8 core_id, uint8 mac_group_id);
extern int32
_sys_at_mac_set_mcmac_init_reg(uint8 lchip, uint8 core_id, uint8 mac_group_id);
extern int32
_sys_at_mac_get_dynamic_switch_list(uint8 lchip, uint16 physical_serdes, sys_dmps_ds_list_t* target);
extern int32
_sys_at_cpumac_set_mac_config(uint8 lchip, uint16 mac_id);
extern int32
_sys_at_mac_set_macshim_pre_group(uint8 lchip, uint8 mac_group_id);
int32
_sys_at_datapath_get_port_chan_by_serdes(uint8 lchip, uint16 logic_serdes, uint16* p_chan, uint16* p_dport);
int32
_sys_at_qmgr_speed_to_credit(uint8 lchip, uint16 speed);
int32
_sys_at_datapath_bufretrv_get_credit(uint8 lchip, uint32 speed, sys_datapath_bufsz_step_t *step, uint8 prio);
int32
 _sys_at_datapath_epe_speed_to_credit(uint16 speed);
int32
_sys_at_nettx_speed_to_credit(uint8 lchip, uint16 speed);
int32
_sys_at_calendar_speed_info_collect(uint8 lchip, sys_at_cal_info_collect_t cal_info[],
                                    uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 dp_txqm_id, uint8 cal_type);
int32
_sys_at_datapath_qmgr_common_calendar(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 *p_error,
                                        uint16 *p_walk_end, uint16 *p_cal, sys_at_cal_info_collect_t* cal_info);
int32
_sys_at_datapath_nettx_common_calendar(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 dp_txqm_id,
                                        uint8 *p_error, uint16 *p_walk_end, uint16 *p_cal, sys_at_cal_info_collect_t* cal_info);
int32
_sys_at_datapath_calculate_general_calendar_parser(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 is_cpumac_cal,
                                                    uint16* cal, uint16* walk_end, sys_at_cal_info_collect_t* cal_info);
int32
_sys_at_datapath_dynamic_switch_dp(uint8 lchip, sys_dmps_ds_list_t* target, uint8 dir_flag);
int32
_sys_at_datapath_get_misc_loop_chan(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint16 sub_chan_id, uint16* chan_id, uint8 dir_bmp);
int32
_sys_at_datapath_set_qmgr_deq_scan_bmp(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 pp_chan, uint32 value);
int32 
_sys_at_datapath_serdes_clktree_cpumac_cfg(uint8 lchip, uint16 lsd, uint8 mode);

#ifdef DRV_IOW_FIELD
#undef DRV_IOW_FIELD
#define DRV_IOW_FIELD(lchip, memid, inst_id, fieldid, value, ptr) \
    do\
    {\
        int32 retv = 0;\
        char   fld_str[64] = {0};\
        retv = drv_set_field(lchip, memid, fieldid, ptr, value);\
        if (retv < 0)\
        {\
            return(retv); \
        }\
        drv_usw_get_field_string_by_id(lchip, memid, fieldid, fld_str);\
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw))\
        {\
            sal_fprintf(g_tm_dump_fp, "write %-35s 0 inst %-5d field: %-45s 0x%x\n", \
                TABLE_NAME(lchip, memid), inst_id, fld_str, *value); \
        }\
    }\
    while(0)

#endif

/* DRV_IOW_FIELD extender, for index Not Zero */
#define DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, memid, inst_id, fieldid, value, ptr) \
    do\
    {\
        int32 retv = 0;\
        char   fld_str[64] = {0};\
        retv = drv_set_field(lchip, memid, fieldid, ptr, value);\
        if (retv < 0)\
        {\
            return(retv); \
        }\
        drv_usw_get_field_string_by_id(lchip, memid, fieldid, fld_str);\
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw))\
        {\
            if ((255 != pp_id) && (255 != dp_id))\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s 0 %-45s 0x%x inst %-5d core %u pp %u dp %u\n", \
                TABLE_NAME(lchip, memid), fld_str, *value, inst_id, core_id, pp_id, dp_id); \
            }\
            else if ((255 != pp_id))\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s 0 %-45s 0x%x inst %-5d core %u pp %u\n", \
                TABLE_NAME(lchip, memid), fld_str, *value, inst_id, core_id, pp_id); \
            }\
            else\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s 0 %-45s 0x%x inst %-5d core %u\n", \
                TABLE_NAME(lchip, memid), fld_str, *value, inst_id, core_id); \
            }\
        }\
    }\
    while(0)

#define DRV_IOW_ENTRY(lchip, memid, inst_id, entry_id, fieldid, value, ptr) \
    do\
    {\
        int32 retv = 0;\
        char   fld_str[64] = {0};\
        retv = drv_set_field(lchip, memid, fieldid, ptr, value);\
        if (retv < 0)\
        {\
            return(retv); \
        }\
        drv_usw_get_field_string_by_id(lchip, memid, fieldid, fld_str);\
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw))\
        {\
            sal_fprintf(g_tm_dump_fp, "write %-35s %-5d %-45s 0x%x inst %-5d\n", \
                TABLE_NAME(lchip, memid), entry_id, fld_str, *value, inst_id); \
        }\
    }\
    while(0)

#define DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, memid, inst_id, entry_id, fieldid, value, ptr) \
    do\
    {\
        int32 retv = 0;\
        char   fld_str[64] = {0};\
        retv = drv_set_field(lchip, memid, fieldid, ptr, value);\
        if (retv < 0)\
        {\
            return(retv); \
        }\
        drv_usw_get_field_string_by_id(lchip, memid, fieldid, fld_str);\
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw))\
        {\
            if ((255 != pp_id) && (255 != dp_id))\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s %-5d %-45s 0x%x inst %-5d core %u pp %u dp %u\n", \
                    TABLE_NAME(lchip, memid), entry_id, fld_str, *value, inst_id, core_id, pp_id, dp_id); \
            }\
            else if ((255 != pp_id))\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s %-5d %-45s 0x%x inst %-5d core %u pp %u\n", \
                    TABLE_NAME(lchip, memid), entry_id, fld_str, *value, inst_id, core_id, pp_id); \
            }\
            else\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s %-5d %-45s 0x%x inst %-5d core %u\n", \
                    TABLE_NAME(lchip, memid), entry_id, fld_str, *value, inst_id, core_id); \
            }\
        }\
    }\
    while(0)

#define DP_DEBUG_FUNCTION_CALLED_PRINT() \
    do \
    { \
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw)) \
        {\
            sal_fprintf(g_tm_dump_fp, "------ %s enter ----------------\n", __func__); \
        }\
    } \
    while(0)

#define DP_DEBUG_FUNCTION_RETURN_PRINT() \
    do \
    { \
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw)) \
        {\
            sal_fprintf(g_tm_dump_fp, "------ %s return ----------------\n", __func__); \
        }\
    } \
    while(0)

int32
sys_at_datapath_get_extport_start_id(uint8 lchip, uint16* p_lport_start)
{
    *p_lport_start = SYS_INTERNAL_PORT_START;
    return CTC_E_NONE;
}

#ifdef EMULATION_ENV
extern uint32 g_drv_oper_bmp;
#endif

#ifdef PCS_ONLY

int32
_sys_at_datapath_nettx_register(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint32 cmd     = 0;
    uint32 value   = 0;
    //uint32 index  = 0;
    NetTxCalCtl_m nettx_cal_ctl;
    NetTxMiscCtl_m nettx_misc_ctl;

    /* NetTxCalCtl */
    cmd = DRV_IOR(NetTxCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, 0, core_id, pp_id, dp_id, cmd, &nettx_cal_ctl));
    //SYS_AT_SPEED_MODE_TO_NETTX_WALKER_END(speed_mode, value);
    value = 0x7;
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, NetTxCalCtl_t, 0, NetTxCalCtl_walkerEnd0_f, &value, &nettx_cal_ctl);
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, NetTxCalCtl_t, 0, NetTxCalCtl_walkerEnd1_f, &value, &nettx_cal_ctl);
    cmd = DRV_IOW(NetTxCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, 0, core_id, pp_id, dp_id, cmd, &nettx_cal_ctl));

    /* NetTxMiscCtl */
    cmd = DRV_IOR(NetTxMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, 0, core_id, pp_id, dp_id, cmd, &nettx_misc_ctl));
    //SYS_AT_SPEED_MODE_TO_NETTX_READY(speed_mode, value);
    value = 0x1;
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, NetTxMiscCtl_t, 0, NetTxMiscCtl_netTxReady_f, &value, &nettx_misc_ctl);
    cmd = DRV_IOW(NetTxMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, 0, core_id, pp_id, dp_id, cmd, &nettx_misc_ctl));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_nettx_credit(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id,
                                    uint8 sub_chan_id, uint8 speed_mode)
{
    uint32 cmd     = 0;
    uint32 value   = 0;
    uint32 index   = 0;
    uint32 credit  = 0;
    uint32 speed   = 0;
    //NetTxCreditThrd_m nettx_credit_thrd;

    SYS_AT_SPEED_MODE_TO_SPEED_VALUE(speed_mode, speed);
    SYS_AT_NETTX_SPEED_TO_CREDIT(speed, credit);

    index = DRV_INS(0, sub_chan_id);
    value = credit;
    //DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, NetTxCreditThrd_t, index, NetTxMiscCtl_netTxReady_f, &value, &nettx_credit_thrd);
    cmd = DRV_IOW(NetTxCreditThrd_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &value));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write %-50s dp %-15d offset %-15d  0x%-30X\n", "NetTxCreditThrd_t",
        dp_id, sub_chan_id, value);

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_nettx_thrd(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id,
                                    uint8 sub_chan_id, uint8 speed_mode)
{
    uint32 cmd     = 0;
    uint32 value   = 0;
    uint32 index   = 0;
    //NetTxUcTxThrdCfg_m nettx_thrd_cfg;

    /* TBD: calculate cfg value */
    SYS_AT_SPEED_MODE_TO_NETTX_THRD(speed_mode, value);

    index  = DRV_INS(0, sub_chan_id);
    //value = 0x00030005; // 50G
    //DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, NetTxUcTxThrdCfg_t, index, NetTxMiscCtl_netTxReady_f, &value, &nettx_thrd_cfg);
    cmd = DRV_IOW(NetTxUcTxThrdCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &value));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write %-50s dp %-15d offset %-15d  0x%-30X\n", "NetTxUcTxThrdCfg_t",
        dp_id, sub_chan_id, value);

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_nettx_timer_thrd(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id,
                                        uint8 sub_chan_id, uint8 speed_mode)
{
    uint32 cmd     = 0;
    uint32 value   = 0;
    uint32 index   = 0;
    //NetTxUcTxThrdCfg_m nettx_thrd_cfg;

    /* TBD: calculate cfg value */
    SYS_AT_SPEED_MODE_TO_NETTX_TIMER_THRD(speed_mode, value);

    index  = DRV_INS(0, sub_chan_id);
    //value = 0x0000008c; // 10G
    //DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, NetTxUcTxThrdCfg_t, index, NetTxMiscCtl_netTxReady_f, &value, &nettx_thrd_cfg);
    cmd = DRV_IOW(NetTxUcTxTimerThrdCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &value));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write %-50s dp %-15d offset %-15d  0x%-30X\n", "NetTxUcTxTimerThrdCfg_t",
        dp_id, sub_chan_id, value);

    return CTC_E_NONE;
}
#endif

uint8
_sys_at_datapath_is_same_core_pp_dp_txqm(uint8 lchip, uint16 chan_id, 
                                                uint8 core_id_s, uint8 pp_id_s, uint8 dp_id_s, uint8 txqm_id_s, uint8 dir_bmp)
{
    uint8 core_id = 0;
    uint8 pp_id   = 0;
    uint8 dp_id   = 0;
    uint8 txqm_id = 0;
    uint8 is_same = TRUE;
    
    SYS_CONDITION_RETURN(CTC_E_NONE != sys_usw_dmps_db_get_core_pp_dp_txqm_by_chan(lchip, chan_id, 
        &core_id, &pp_id, &dp_id, &txqm_id, dir_bmp), FALSE);

    if(is_same && (SYS_DMPS_INVALID_U8 != core_id_s) && (core_id != core_id_s))
    {
        is_same = FALSE;
    }
    if(is_same && (SYS_DMPS_INVALID_U8 != pp_id_s) && (pp_id != pp_id_s))
    {
        is_same = FALSE;
    }
    if(is_same && (SYS_DMPS_INVALID_U8 != dp_id_s) && (dp_id != dp_id_s))
    {
        is_same = FALSE;
    }
    if(is_same && (SYS_DMPS_INVALID_U8 != txqm_id_s) && (txqm_id != txqm_id_s))
    {
        is_same = FALSE;
    }

    return is_same;
}

int32
_sys_at_datapath_map_sub_chan_mc(uint8 lchip, uint8 priority, uint16 chan_id, uint16 sub_chan, uint8 dir_bmp)
{
    uint8  core_id   = 0;
    uint8  core_num  = 0;
    uint8  pp_id     = 0;
    uint8  core_temp = 0;
    uint32 cmd       = 0;
    uint32 value     = 0;
    uint32 index     = 0;
    sys_dmps_db_upt_info_t port_info = {0};
    McQWritePortChannelMap_m mc_q_write_portchanmap;

    core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

    if (CHAN_DIR_IS_TX(dir_bmp))
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID,                 chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,       core_id);

        /* write local core */
        core_temp = core_id;

        for (pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));

            /* McQWritePortChannelMap, priority index */
            value = sub_chan & 0xff;
            index = DRV_INS(0, (chan_id >> 2) + 128 * priority);
            cmd   = DRV_IOR(McQWritePortChannelMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_temp, pp_id, cmd, &mc_q_write_portchanmap));

            DRV_IOW_ENTRY_NZ(core_temp, pp_id, 0xff, lchip, McQWritePortChannelMap_t, 0, (chan_id >> 2) + 128 * priority,
                (McQWritePortChannelMap_g_0_channelId_f + (chan_id & 0x3)), &value, &mc_q_write_portchanmap);

            cmd   = DRV_IOW(McQWritePortChannelMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_temp, pp_id, cmd, &mc_q_write_portchanmap));
        }

        if (1 == core_num)
        {
            return CTC_E_NONE;
        }

        /* write remote core */
        core_temp = (0 == core_id) ? 1 : 0;

        for (pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));

            /* McQWritePortChannelMap, priority index */
            value = sub_chan | 0x100;
            index = DRV_INS(0, (chan_id >> 2) + 128 * priority);
            cmd   = DRV_IOR(McQWritePortChannelMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_temp, pp_id, cmd, &mc_q_write_portchanmap));

            DRV_IOW_ENTRY_NZ(core_temp, pp_id, 0xff, lchip, McQWritePortChannelMap_t, 0, (chan_id >> 2) + 128 * priority,
                (McQWritePortChannelMap_g_0_channelId_f + (chan_id & 0x3)), &value, &mc_q_write_portchanmap);

            cmd   = DRV_IOW(McQWritePortChannelMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_temp, pp_id, cmd, &mc_q_write_portchanmap));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_map_sub_chan_uc(uint8 lchip, uint8 priority, uint16 chan_id, uint16 sub_chan, uint8 dir_bmp)
{
    uint8  core_id   = 0;
    uint8  core_num  = 0;
    uint8  pp_id     = 0;
    uint8  core_temp = 0;
    uint32 cmd       = 0;
    uint32 value     = 0;
    uint32 index     = 0;
    uint32 step      = 0;
    sys_dmps_db_upt_info_t port_info = {0};
    UcQWritePortChannelMap_m uc_q_write_portchanmap;

    core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

    if (CHAN_DIR_IS_TX(dir_bmp))
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID,                 chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,       core_id);

        /* write local core */
        core_temp = core_id;

        for (pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));

            /* UcQWritePortChannelMap */
            index = DRV_INS(0, chan_id);
            cmd   = DRV_IOR(UcQWritePortChannelMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_temp, pp_id, cmd, &uc_q_write_portchanmap));

            value = sub_chan & 0xff;
            step  = UcQWritePortChannelMap_g_1_channelId_f - UcQWritePortChannelMap_g_0_channelId_f;
            DRV_IOW_ENTRY_NZ(core_temp, pp_id, 0xff, lchip, UcQWritePortChannelMap_t, 0, chan_id,
                UcQWritePortChannelMap_g_0_channelId_f + priority * step, &value, &uc_q_write_portchanmap);

            cmd   = DRV_IOW(UcQWritePortChannelMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_temp, pp_id, cmd, &uc_q_write_portchanmap));
        }

        if (1 == core_num)
        {
            return CTC_E_NONE;
        }

        /* write remote core */
        core_temp = (0 == core_id) ? 1 : 0;

        for (pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));

            /* UcQWritePortChannelMap */
            index = DRV_INS(0, chan_id);
            cmd   = DRV_IOR(UcQWritePortChannelMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_temp, pp_id, cmd, &uc_q_write_portchanmap));

            value = sub_chan | 0x100;
            step  = UcQWritePortChannelMap_g_1_channelId_f - UcQWritePortChannelMap_g_0_channelId_f;
            DRV_IOW_ENTRY_NZ(core_temp, pp_id, 0xff, lchip, UcQWritePortChannelMap_t, 0, chan_id,
                UcQWritePortChannelMap_g_0_channelId_f + priority * step, &value, &uc_q_write_portchanmap);

            cmd   = DRV_IOW(UcQWritePortChannelMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_temp, pp_id, cmd, &uc_q_write_portchanmap));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_map_nw_chan(uint8 lchip, uint8 core, uint8 core_id, uint8 pp_id, uint8 dp_id, uint16 sub_chan_id, uint16 chan_id, uint8 dir_bmp)
{
    uint8  is_remote = 0;
    uint8  core_dp   = 0;
    uint32 entry     = 0;
    uint32 cmd       = 0;
    uint32 value     = 0;
    uint32 index     = 0;
    DsErmChannelPortMap_m ds_erm_map;
    DsXfcChannelPortMap_m ds_xfc_map;

    core_dp   = pp_id * SYS_AT_DP_NUM_PER_PP + dp_id;
    is_remote = (core == core_id) ? 0 : 1;

    if (sub_chan_id & 0x10) /* sub_chan_id: 16-23 */
    {
        /* local core: 128-159, remote core: 160-191 */
        /* entry = 128 + 32 * is_remote + core_dp * 4 + (sub_chan_id - 16) / 2 */
        entry = 128 + 32 * is_remote + (core_dp << 2) + ((sub_chan_id - 16) >> 1);
        //entry = 128 + 32 * is_remote + (((nw_chan >> 1) / 12) << 2) + ((nw_chan >> 1) % 12 - 8);
    }
    else    /* sub_chan_id: 0-15 */
    {
        /* local core: 0-63, remote core: 64-127 */
        /* entry = 64 * is_remote + core_dp * 8 + sub_chan_id / 2 */
        entry = 64 * is_remote + (core_dp << 3) + (sub_chan_id >> 1);
        //entry = 64 * is_remote + (((nw_chan >> 1) / 12) << 3) + (nw_chan >> 1) % 12;
    }

    if (CHAN_DIR_IS_TX(dir_bmp))
    {
        /* DsErmChannelPortMap */
        index = DRV_INS(0, entry);
        cmd   = DRV_IOR(DsErmChannelPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &ds_erm_map));

        value = chan_id;
        DRV_IOW_ENTRY_NZ(core, 0xff, 0xff, lchip, DsErmChannelPortMap_t, 0, entry,
            ((sub_chan_id % 2) ? DsErmChannelPortMap_g_1_ppDestPort_f : DsErmChannelPortMap_g_0_ppDestPort_f), &value, &ds_erm_map);

        cmd   = DRV_IOW(DsErmChannelPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &ds_erm_map));

        /* DsXfcChannelPortMap */
        index = DRV_INS(0, entry);
        cmd   = DRV_IOR(DsXfcChannelPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &ds_xfc_map));

        value = chan_id;
        DRV_IOW_ENTRY_NZ(core, 0xff, 0xff, lchip, DsXfcChannelPortMap_t, 0, entry,
            ((sub_chan_id % 2) ? DsXfcChannelPortMap_g_1_ppPort_f : DsXfcChannelPortMap_g_0_ppPort_f), &value, &ds_xfc_map);

        cmd   = DRV_IOW(DsXfcChannelPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &ds_xfc_map));
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_map_all_pp_by_port(uint8 lchip, uint16 dport, uint16 chan_id, uint8 dir_bmp)
{
    uint8  pp_id    = 0;
    uint8  core     = 0;
    uint8  core_num = 0;
    uint32 cmd      = 0;
    uint32 value    = 0;
    uint32 index    = 0;
    DsIpeFwdDestPortMap_m           ipefwd_portmap;
    DsMcQWriteDestPortMap_m         mcq_portmap;

    core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

    for (core = 0; core < core_num; core++)
    {
        for (pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core, pp_id));

            if (CHAN_DIR_IS_RX(dir_bmp))
            {
                /* DsIpeFwdDestPortMap */
                index = DRV_INS(0, dport);
                cmd   = DRV_IOR(DsIpeFwdDestPortMap_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &ipefwd_portmap));

                value = chan_id;
                DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, DsIpeFwdDestPortMap_t, 0, dport, DsIpeFwdDestPortMap_ppDestPort_f, &value, &ipefwd_portmap);

                cmd   = DRV_IOW(DsIpeFwdDestPortMap_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &ipefwd_portmap));
            }

            if (CHAN_DIR_IS_TX(dir_bmp))
            {
                /* DsMcQWriteDestPortMap */
                index = DRV_INS(0, dport);
                cmd   = DRV_IOR(DsMcQWriteDestPortMap_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &mcq_portmap));

                value = chan_id;
                DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, DsMcQWriteDestPortMap_t, 0, dport, DsMcQWriteDestPortMap_ppDestPort_f, &value, &mcq_portmap);

                cmd   = DRV_IOW(DsMcQWriteDestPortMap_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &mcq_portmap));
            }
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_map_all_pp_by_chan(uint8 lchip, uint16 dport, uint16 chan_id, uint8 dir_bmp)
{
    uint8  pp_id    = 0;
    uint8  core     = 0;
    uint8  core_num = 0;
    uint32 cmd      = 0;
    uint32 value    = 0;
    uint32 index    = 0;
    IpeHeaderAdjustPhyPortMap_m     ipe_phy_port_map;
    EpeHeaderAdjustPhyPortMap_m     epe_phy_port_map;

    core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

    for (core = 0; core < core_num; core++)
    {
        for (pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core, pp_id));

            if (CHAN_DIR_IS_RX(dir_bmp))
            {
                /* IpeHeaderAdjustPhyPortMap */
                index = DRV_INS(0, chan_id);
                cmd   = DRV_IOR(IpeHeaderAdjustPhyPortMap_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &ipe_phy_port_map));

                value = dport;
                DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, IpeHeaderAdjustPhyPortMap_t, 0, chan_id,
                    IpeHeaderAdjustPhyPortMap_localPhyPort_f, &value, &ipe_phy_port_map);

                cmd   = DRV_IOW(IpeHeaderAdjustPhyPortMap_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &ipe_phy_port_map));
            }

            if (CHAN_DIR_IS_TX(dir_bmp))
            {
                /* EpeHeaderAdjustPhyPortMap */
                index = DRV_INS(0, chan_id);
                cmd   = DRV_IOR(EpeHeaderAdjustPhyPortMap_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &epe_phy_port_map));

                value = dport;
                DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, EpeHeaderAdjustPhyPortMap_t, 0, chan_id,
                    EpeHeaderAdjustPhyPortMap_localPhyPort_f, &value, &epe_phy_port_map);

                cmd   = DRV_IOW(EpeHeaderAdjustPhyPortMap_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &epe_phy_port_map));
            }
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_map_chan(uint8 lchip, uint16 chan_id, uint8 dir_bmp)
{
    uint8  dp_id         = 0;
    uint8  core_id       = 0;
    uint8  pp_id         = 0;
    uint8  mac_client_id = 0;
    uint8  flag          = FALSE;
    uint16 sub_chan_id   = 0;
    uint32 cmd           = 0;
    uint32 value         = 0;
    uint32 index         = 0;
    sys_dmps_db_chan_info_t chan_info = {0};
    IpeHeaderAdjustChannelPortMap_m ipe_chan_port;
    EpeHeaderAdjustChannelPortMap_m epe_chan_port;
    DsEpeHeaderEditChannelPortMap_m dsepe_map;
    EpeScheduleChanToPortRa_m       chan_to_port;
    EpeSchedulePortToChanRa_m       port_to_chan;
    DsNetRxPortToChanMap_m          netrx_port_to_chan;
    DsNetRxChanToPortMap_m          netrx_chan_to_port;

    chan_info.chan_id = chan_id;

    if (CHAN_DIR_IS_RX(dir_bmp))
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, &chan_info, CHAN_DIR_RX));
        if (SYS_DMPS_INVALID_SUB_CHAN_ID == chan_info.sub_chan_id)
        {
            return CTC_E_NONE;
        }
        core_id       = chan_info.core_id;
        pp_id         = chan_info.pp_id;
        dp_id         = chan_info.dp_id;
        sub_chan_id   = chan_info.sub_chan_id;
        mac_client_id = chan_info.mac_client_id;

        if (!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id))
        {
            return CTC_E_NONE;
        }

        /* IpeHeaderAdjustChannelPortMap */
        index = DRV_INS(0, sub_chan_id);
        cmd   = DRV_IOR(IpeHeaderAdjustChannelPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &ipe_chan_port));

        value = chan_id;
        DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeHeaderAdjustChannelPortMap_t, 0, sub_chan_id,
            (0 == dp_id) ? IpeHeaderAdjustChannelPortMap_g_0_ppSrcPort_f : IpeHeaderAdjustChannelPortMap_g_1_ppSrcPort_f, &value, &ipe_chan_port);

        cmd   = DRV_IOW(IpeHeaderAdjustChannelPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &ipe_chan_port));

        CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_uc(lchip, 0, chan_id,
            ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (sub_chan_id & 0x1F), CHAN_DIR_TXRX));
        CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_uc(lchip, 1, chan_id,
            ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (sub_chan_id & 0x1F), CHAN_DIR_TXRX));
        CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_uc(lchip, 2, chan_id,
            ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (sub_chan_id & 0x1F), CHAN_DIR_TXRX));
        CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_mc(lchip, 0, chan_id,
            ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (sub_chan_id & 0x1F), CHAN_DIR_TXRX));
        CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_mc(lchip, 1, chan_id,
            ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (sub_chan_id & 0x1F), CHAN_DIR_TXRX));
        flag = TRUE;

        /* network chan map */
        if (SYS_AT_IS_NW_CHAN(sub_chan_id))
        {
            /*netrx mac_client to channel*/
            index = DRV_INS(0, mac_client_id);
            cmd  = DRV_IOR(DsNetRxPortToChanMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &netrx_port_to_chan));
            value = sub_chan_id;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, DsNetRxPortToChanMap_t, 0, mac_client_id,
                DsNetRxPortToChanMap_chan_f, &value, &netrx_port_to_chan);
            cmd = DRV_IOW(DsNetRxPortToChanMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &netrx_port_to_chan));

            /*netrx channel to mac_client*/
            index = DRV_INS(0, sub_chan_id);
            cmd = DRV_IOR(DsNetRxChanToPortMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &netrx_chan_to_port));
            value = mac_client_id;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, DsNetRxChanToPortMap_t, 0, sub_chan_id,
                DsNetRxChanToPortMap_portId_f, &value, &netrx_chan_to_port);
            cmd = DRV_IOW(DsNetRxChanToPortMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &netrx_chan_to_port));
        }
    }

    if (CHAN_DIR_IS_TX(dir_bmp))
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, &chan_info, CHAN_DIR_TX));
        if (SYS_DMPS_INVALID_SUB_CHAN_ID == chan_info.sub_chan_id)
        {
            return CTC_E_NONE;
        }
        core_id       = chan_info.core_id;
        pp_id         = chan_info.pp_id;
        dp_id         = chan_info.dp_id;
        sub_chan_id   = chan_info.sub_chan_id;
        mac_client_id = chan_info.mac_client_id;

        if (!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id))
        {
            return CTC_E_NONE;
        }

        /* EpeHeaderAdjustChannelPortMap */
        index = DRV_INS(0, sub_chan_id);
        cmd   = DRV_IOR(EpeHeaderAdjustChannelPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &epe_chan_port));
        value = chan_id;
        DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, EpeHeaderAdjustChannelPortMap_t, 0, sub_chan_id,
            (0 == dp_id) ? EpeHeaderAdjustChannelPortMap_g_0_ppDestPort_f : EpeHeaderAdjustChannelPortMap_g_1_ppDestPort_f, &value, &epe_chan_port);
        cmd   = DRV_IOW(EpeHeaderAdjustChannelPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &epe_chan_port));

        /* DsEpeHeaderEditChannelPortMap */
        index = DRV_INS(0, sub_chan_id);
        cmd   = DRV_IOR(DsEpeHeaderEditChannelPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &dsepe_map));
        value = chan_id;
        DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, DsEpeHeaderEditChannelPortMap_t, 0, sub_chan_id,
            (0 == dp_id) ? DsEpeHeaderEditChannelPortMap_g_0_ppDestPort_f : DsEpeHeaderEditChannelPortMap_g_1_ppDestPort_f, &value, &dsepe_map);
        cmd = DRV_IOW(DsEpeHeaderEditChannelPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &dsepe_map));

        /* EpeScheduleChanToPortRa */
        index = DRV_INS(0, sub_chan_id);
        cmd   = DRV_IOR(EpeScheduleChanToPortRa_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &chan_to_port));
        value = mac_client_id;
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, EpeScheduleChanToPortRa_t, 0, sub_chan_id,
            EpeScheduleChanToPortRa_physicalPortId_f, &value, &chan_to_port);
        cmd   = DRV_IOW(EpeScheduleChanToPortRa_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &chan_to_port));

        /* EpeSchedulePortToChanRa */
        index = DRV_INS(0, mac_client_id);
        cmd   = DRV_IOR(EpeSchedulePortToChanRa_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &port_to_chan));
        value = sub_chan_id;
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, EpeSchedulePortToChanRa_t, 0, mac_client_id,
            EpeSchedulePortToChanRa_internalChanId_f, &value, &port_to_chan);
        cmd   = DRV_IOW(EpeSchedulePortToChanRa_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &port_to_chan));

        if (!flag)
        {
            CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_uc(lchip, 0, chan_id,
                ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (sub_chan_id & 0x1F), CHAN_DIR_TXRX));
            CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_uc(lchip, 1, chan_id,
                ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (sub_chan_id & 0x1F), CHAN_DIR_TXRX));
            CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_uc(lchip, 2, chan_id,
                ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (sub_chan_id & 0x1F), CHAN_DIR_TXRX));
            CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_mc(lchip, 0, chan_id,
                ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (sub_chan_id & 0x1F), CHAN_DIR_TXRX));
            CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_mc(lchip, 1, chan_id,
                ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (sub_chan_id & 0x1F), CHAN_DIR_TXRX));
        }

        /* network chan map */
        if (SYS_AT_IS_NW_CHAN(sub_chan_id))
        {
            /* local core */
#if(1 == SDK_WORK_PLATFORM)
            (void)(_sys_at_datapath_map_nw_chan(lchip, core_id, core_id, pp_id, dp_id, sub_chan_id, chan_id, dir_bmp));
#else
            CTC_ERROR_RETURN(_sys_at_datapath_map_nw_chan(lchip, core_id, core_id, pp_id, dp_id, sub_chan_id, chan_id, dir_bmp));
#endif

            if (SYS_AT_CHIP_IS_DC(lchip))
            {
                /* remote core */
#if(1 == SDK_WORK_PLATFORM)
                (void)(_sys_at_datapath_map_nw_chan(lchip, 1 - core_id, core_id, pp_id, dp_id, sub_chan_id, chan_id, dir_bmp));
#else
                CTC_ERROR_RETURN(_sys_at_datapath_map_nw_chan(lchip, 1 - core_id, core_id, pp_id, dp_id, sub_chan_id, chan_id, dir_bmp));
#endif
            }
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_map_by_chan(uint8 lchip, uint16 dport, uint16 chan_id, uint8 dir_bmp)
{
    CTC_ERROR_RETURN(_sys_at_datapath_map_chan(lchip, chan_id, dir_bmp));
    if (dport < SYS_USW_MAX_PORT_NUM_PER_CHIP)
    {
        CTC_ERROR_RETURN(_sys_at_datapath_map_all_pp_by_chan(lchip, dport, chan_id, dir_bmp));
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_map_by_port(uint8 lchip, uint16 dport, uint16 chan_id, uint8 dir_bmp)
{
    CTC_ERROR_RETURN(_sys_at_datapath_map_all_pp_by_port(lchip, dport, chan_id, dir_bmp));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_map(uint8 lchip, uint16 dport, uint16 chan_id, uint8 dir_bmp)
{
    CTC_ERROR_RETURN(_sys_at_datapath_map_by_chan(lchip, dport, chan_id, dir_bmp));
    CTC_ERROR_RETURN(_sys_at_datapath_map_by_port(lchip, dport, chan_id, dir_bmp));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_map_pre(uint8 lchip)
{
    uint8  core_id       = 0;
    uint8  core_num      = 0;
    uint8  pp_id         = 0;
    uint16 sub_chan_id   = 0;
    uint32 cmd           = 0;
    uint32 value         = 0;
    uint32 index         = 0;
    IpeHeaderAdjustChannelPortMap_m ipe_chan_port;
    EpeHeaderAdjustChannelPortMap_m epe_chan_port;

    core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

    for (core_id = 0; core_id < core_num; core_id++)
    {
        for (pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));
            for (sub_chan_id = 0; sub_chan_id < SYS_AT_CHAN_NUM_PER_DP; sub_chan_id++)
            {
                /* IpeHeaderAdjustChannelPortMap */
                index = DRV_INS(0, sub_chan_id);
                cmd   = DRV_IOR(IpeHeaderAdjustChannelPortMap_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &ipe_chan_port));

                value = MCHIP_CAP(SYS_CAP_CHANID_ELOG);
                DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeHeaderAdjustChannelPortMap_t, 0, sub_chan_id,
                    IpeHeaderAdjustChannelPortMap_g_2_ppSrcPort_f, &value, &ipe_chan_port);
                value = MCHIP_CAP(SYS_CAP_CHANID_ELOG) + 1;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeHeaderAdjustChannelPortMap_t, 0, sub_chan_id,
                    IpeHeaderAdjustChannelPortMap_g_3_ppSrcPort_f, &value, &ipe_chan_port);

                cmd   = DRV_IOW(IpeHeaderAdjustChannelPortMap_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &ipe_chan_port));

                /* EpeHeaderAdjustChannelPortMap */
                index = DRV_INS(0, sub_chan_id);
                cmd   = DRV_IOR(EpeHeaderAdjustChannelPortMap_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &epe_chan_port));

                value = MCHIP_CAP(SYS_CAP_CHANID_DROP);
                DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, EpeHeaderAdjustChannelPortMap_t, 0, sub_chan_id,
                    EpeHeaderAdjustChannelPortMap_g_0_ppDestPort_f, &value, &epe_chan_port);
                value = MCHIP_CAP(SYS_CAP_CHANID_DROP);
                DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, EpeHeaderAdjustChannelPortMap_t, 0, sub_chan_id,
                    EpeHeaderAdjustChannelPortMap_g_1_ppDestPort_f, &value, &epe_chan_port);

                cmd   = DRV_IOW(EpeHeaderAdjustChannelPortMap_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &epe_chan_port));
            }
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_init_chan_type(uint8 lchip)
{
    uint8  core_id  = 0;
    uint8  pp_id    = 0;
    uint8  dp_id    = 0;
    uint8  core_num = 0;
    uint32 index    = 0;
    uint32 value    = 0;
    uint32 cmd      = 0;
    IpeFwdPortTypeCtl_m      ipe_fwd_ptc;
    IpeHdrAdjPortTypeCtl_m   ipe_hdr_adj_ptc;
    BufferStorePortTypeCtl_m bs_ptc;
    EpeHdrAdjPortTypeCtl_m   epe_ptc;
    McQueWritePortTypeCtl_m  mc_que_ptc;

    core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

    for (core_id = 0; core_id < core_num; core_id++)
    {
        index   = DRV_INS(0, 0);

        for (pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));
            cmd   = DRV_IOR(IpeFwdPortTypeCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &ipe_fwd_ptc));
            value = SYS_AT_CHAN_CPUMAC_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeFwdPortTypeCtl_t, 0, 0, IpeFwdPortTypeCtl_cpu_0_ppPort_f, &value, &ipe_fwd_ptc);
            value = SYS_AT_CHAN_CPUMAC_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeFwdPortTypeCtl_t, 0, 0, IpeFwdPortTypeCtl_cpu_1_ppPort_f, &value, &ipe_fwd_ptc);
            value = SYS_AT_CHAN_DMA_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeFwdPortTypeCtl_t, 0, 0, IpeFwdPortTypeCtl_dma_0_ppPort_f, &value, &ipe_fwd_ptc);
            value = SYS_AT_CHAN_DMA_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeFwdPortTypeCtl_t, 0, 0, IpeFwdPortTypeCtl_dma_1_ppPort_f, &value, &ipe_fwd_ptc);
            value = SYS_AT_CHAN_LOG_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeFwdPortTypeCtl_t, 0, 0, IpeFwdPortTypeCtl_log_0_ppPort_f, &value, &ipe_fwd_ptc);
            value = SYS_AT_CHAN_LOG_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeFwdPortTypeCtl_t, 0, 0, IpeFwdPortTypeCtl_log_1_ppPort_f, &value, &ipe_fwd_ptc);
            value = SYS_AT_CHAN_LOOP_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeFwdPortTypeCtl_t, 0, 0, IpeFwdPortTypeCtl_loop_0_ppPort_f, &value, &ipe_fwd_ptc);
            value = SYS_AT_CHAN_LOOP_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeFwdPortTypeCtl_t, 0, 0, IpeFwdPortTypeCtl_loop_1_ppPort_f, &value, &ipe_fwd_ptc);
            value = SYS_AT_CHAN_NETWORK_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeFwdPortTypeCtl_t, 0, 0, IpeFwdPortTypeCtl_network_0_ppPort_f, &value, &ipe_fwd_ptc);
            value = SYS_AT_CHAN_CPUMAC_NETWORK_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeFwdPortTypeCtl_t, 0, 0, IpeFwdPortTypeCtl_network_1_ppPort_f, &value, &ipe_fwd_ptc);
            value = SYS_AT_CHAN_OAM_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeFwdPortTypeCtl_t, 0, 0, IpeFwdPortTypeCtl_oam_0_ppPort_f, &value, &ipe_fwd_ptc);
            value = SYS_AT_CHAN_OAM_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeFwdPortTypeCtl_t, 0, 0, IpeFwdPortTypeCtl_oam_1_ppPort_f, &value, &ipe_fwd_ptc);
            cmd   = DRV_IOW(IpeFwdPortTypeCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &ipe_fwd_ptc));

            cmd   = DRV_IOR(IpeHdrAdjPortTypeCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &ipe_hdr_adj_ptc));
            value = SYS_AT_CHAN_CPUMAC_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeHdrAdjPortTypeCtl_t, 0, 0, IpeHdrAdjPortTypeCtl_cpu_0_ppPort_f, &value, &ipe_hdr_adj_ptc);
            value = SYS_AT_CHAN_CPUMAC_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeHdrAdjPortTypeCtl_t, 0, 0, IpeHdrAdjPortTypeCtl_cpu_1_ppPort_f, &value, &ipe_hdr_adj_ptc);
            value = SYS_AT_CHAN_DMA_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeHdrAdjPortTypeCtl_t, 0, 0, IpeHdrAdjPortTypeCtl_dma_0_ppPort_f, &value, &ipe_hdr_adj_ptc);
            value = SYS_AT_CHAN_DMA_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeHdrAdjPortTypeCtl_t, 0, 0, IpeHdrAdjPortTypeCtl_dma_1_ppPort_f, &value, &ipe_hdr_adj_ptc);
            value = SYS_AT_CHAN_LOG_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeHdrAdjPortTypeCtl_t, 0, 0, IpeHdrAdjPortTypeCtl_log_0_ppPort_f, &value, &ipe_hdr_adj_ptc);
            value = SYS_AT_CHAN_LOG_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeHdrAdjPortTypeCtl_t, 0, 0, IpeHdrAdjPortTypeCtl_log_1_ppPort_f, &value, &ipe_hdr_adj_ptc);
            value = SYS_AT_CHAN_LOOP_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeHdrAdjPortTypeCtl_t, 0, 0, IpeHdrAdjPortTypeCtl_loop_0_ppPort_f, &value, &ipe_hdr_adj_ptc);
            value = SYS_AT_CHAN_LOOP_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeHdrAdjPortTypeCtl_t, 0, 0, IpeHdrAdjPortTypeCtl_loop_1_ppPort_f, &value, &ipe_hdr_adj_ptc);
            value = SYS_AT_CHAN_NETWORK_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeHdrAdjPortTypeCtl_t, 0, 0, IpeHdrAdjPortTypeCtl_network_0_ppPort_f, &value, &ipe_hdr_adj_ptc);
            value = SYS_AT_CHAN_CPUMAC_NETWORK_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeHdrAdjPortTypeCtl_t, 0, 0, IpeHdrAdjPortTypeCtl_network_1_ppPort_f, &value, &ipe_hdr_adj_ptc);
            value = SYS_AT_CHAN_OAM_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeHdrAdjPortTypeCtl_t, 0, 0, IpeHdrAdjPortTypeCtl_oam_0_ppPort_f, &value, &ipe_hdr_adj_ptc);
            value = SYS_AT_CHAN_OAM_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, IpeHdrAdjPortTypeCtl_t, 0, 0, IpeHdrAdjPortTypeCtl_oam_1_ppPort_f, &value, &ipe_hdr_adj_ptc);
            cmd   = DRV_IOW(IpeHdrAdjPortTypeCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &ipe_hdr_adj_ptc));

            for (dp_id = 0; dp_id < SYS_AT_DP_NUM_PER_PP; dp_id++)
            {
                cmd   = DRV_IOR(BufferStorePortTypeCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &bs_ptc));
                value = SYS_AT_CHAN_CPUMAC_START;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, pp_id, lchip, BufferStorePortTypeCtl_t, 0, 0, BufferStorePortTypeCtl_cpu_0_ppPort_f, &value, &bs_ptc);
                value = SYS_AT_CHAN_CPUMAC_END;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, pp_id, lchip, BufferStorePortTypeCtl_t, 0, 0, BufferStorePortTypeCtl_cpu_1_ppPort_f, &value, &bs_ptc);
                value = SYS_AT_CHAN_DMA_START;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, pp_id, lchip, BufferStorePortTypeCtl_t, 0, 0, BufferStorePortTypeCtl_dma_0_ppPort_f, &value, &bs_ptc);
                value = SYS_AT_CHAN_DMA_END;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, pp_id, lchip, BufferStorePortTypeCtl_t, 0, 0, BufferStorePortTypeCtl_dma_1_ppPort_f, &value, &bs_ptc);
                value = SYS_AT_CHAN_LOG_START;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, pp_id, lchip, BufferStorePortTypeCtl_t, 0, 0, BufferStorePortTypeCtl_log_0_ppPort_f, &value, &bs_ptc);
                value = SYS_AT_CHAN_LOG_END;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, pp_id, lchip, BufferStorePortTypeCtl_t, 0, 0, BufferStorePortTypeCtl_log_1_ppPort_f, &value, &bs_ptc);
                value = SYS_AT_CHAN_LOOP_START;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, pp_id, lchip, BufferStorePortTypeCtl_t, 0, 0, BufferStorePortTypeCtl_loop_0_ppPort_f, &value, &bs_ptc);
                value = SYS_AT_CHAN_LOOP_END;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, pp_id, lchip, BufferStorePortTypeCtl_t, 0, 0, BufferStorePortTypeCtl_loop_1_ppPort_f, &value, &bs_ptc);
                value = SYS_AT_CHAN_NETWORK_START;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, pp_id, lchip, BufferStorePortTypeCtl_t, 0, 0, BufferStorePortTypeCtl_network_0_ppPort_f, &value, &bs_ptc);
                value = SYS_AT_CHAN_CPUMAC_NETWORK_END;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, pp_id, lchip, BufferStorePortTypeCtl_t, 0, 0, BufferStorePortTypeCtl_network_1_ppPort_f, &value, &bs_ptc);
                value = SYS_AT_CHAN_OAM_START;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, pp_id, lchip, BufferStorePortTypeCtl_t, 0, 0, BufferStorePortTypeCtl_oam_0_ppPort_f, &value, &bs_ptc);
                value = SYS_AT_CHAN_OAM_END;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, pp_id, lchip, BufferStorePortTypeCtl_t, 0, 0, BufferStorePortTypeCtl_oam_1_ppPort_f, &value, &bs_ptc);
                cmd   = DRV_IOW(BufferStorePortTypeCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &bs_ptc));
            }

            cmd   = DRV_IOR(EpeHdrAdjPortTypeCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &epe_ptc));
            value = SYS_AT_CHAN_CPUMAC_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, EpeHdrAdjPortTypeCtl_t, 0, 0, EpeHdrAdjPortTypeCtl_cpu_0_ppPort_f, &value, &epe_ptc);
            value = SYS_AT_CHAN_CPUMAC_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, EpeHdrAdjPortTypeCtl_t, 0, 0, EpeHdrAdjPortTypeCtl_cpu_1_ppPort_f, &value, &epe_ptc);
            value = SYS_AT_CHAN_DMA_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, EpeHdrAdjPortTypeCtl_t, 0, 0, EpeHdrAdjPortTypeCtl_dma_0_ppPort_f, &value, &epe_ptc);
            value = SYS_AT_CHAN_DMA_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, EpeHdrAdjPortTypeCtl_t, 0, 0, EpeHdrAdjPortTypeCtl_dma_1_ppPort_f, &value, &epe_ptc);
            value = SYS_AT_CHAN_LOG_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, EpeHdrAdjPortTypeCtl_t, 0, 0, EpeHdrAdjPortTypeCtl_log_0_ppPort_f, &value, &epe_ptc);
            value = SYS_AT_CHAN_LOG_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, EpeHdrAdjPortTypeCtl_t, 0, 0, EpeHdrAdjPortTypeCtl_log_1_ppPort_f, &value, &epe_ptc);
            value = SYS_AT_CHAN_LOOP_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, EpeHdrAdjPortTypeCtl_t, 0, 0, EpeHdrAdjPortTypeCtl_loop_0_ppPort_f, &value, &epe_ptc);
            value = SYS_AT_CHAN_LOOP_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, EpeHdrAdjPortTypeCtl_t, 0, 0, EpeHdrAdjPortTypeCtl_loop_1_ppPort_f, &value, &epe_ptc);
            value = SYS_AT_CHAN_NETWORK_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, EpeHdrAdjPortTypeCtl_t, 0, 0, EpeHdrAdjPortTypeCtl_network_0_ppPort_f, &value, &epe_ptc);
            value = SYS_AT_CHAN_CPUMAC_NETWORK_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, EpeHdrAdjPortTypeCtl_t, 0, 0, EpeHdrAdjPortTypeCtl_network_1_ppPort_f, &value, &epe_ptc);
            value = SYS_AT_CHAN_OAM_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, EpeHdrAdjPortTypeCtl_t, 0, 0, EpeHdrAdjPortTypeCtl_oam_0_ppPort_f, &value, &epe_ptc);
            value = SYS_AT_CHAN_OAM_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, EpeHdrAdjPortTypeCtl_t, 0, 0, EpeHdrAdjPortTypeCtl_oam_1_ppPort_f, &value, &epe_ptc);
            cmd   = DRV_IOW(EpeHdrAdjPortTypeCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &epe_ptc));

            cmd   = DRV_IOR(McQueWritePortTypeCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &mc_que_ptc));
            value = SYS_AT_CHAN_CPUMAC_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, McQueWritePortTypeCtl_t, 0, 0, McQueWritePortTypeCtl_cpu_0_ppPort_f, &value, &mc_que_ptc);
            value = SYS_AT_CHAN_CPUMAC_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, McQueWritePortTypeCtl_t, 0, 0, McQueWritePortTypeCtl_cpu_1_ppPort_f, &value, &mc_que_ptc);
            value = SYS_AT_CHAN_DMA_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, McQueWritePortTypeCtl_t, 0, 0, McQueWritePortTypeCtl_dma_0_ppPort_f, &value, &mc_que_ptc);
            value = SYS_AT_CHAN_DMA_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, McQueWritePortTypeCtl_t, 0, 0, McQueWritePortTypeCtl_dma_1_ppPort_f, &value, &mc_que_ptc);
            value = SYS_AT_CHAN_LOG_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, McQueWritePortTypeCtl_t, 0, 0, McQueWritePortTypeCtl_log_0_ppPort_f, &value, &mc_que_ptc);
            value = SYS_AT_CHAN_LOG_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, McQueWritePortTypeCtl_t, 0, 0, McQueWritePortTypeCtl_log_1_ppPort_f, &value, &mc_que_ptc);
            value = SYS_AT_CHAN_LOOP_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, McQueWritePortTypeCtl_t, 0, 0, McQueWritePortTypeCtl_loop_0_ppPort_f, &value, &mc_que_ptc);
            value = SYS_AT_CHAN_LOOP_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, McQueWritePortTypeCtl_t, 0, 0, McQueWritePortTypeCtl_loop_1_ppPort_f, &value, &mc_que_ptc);
            value = SYS_AT_CHAN_NETWORK_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, McQueWritePortTypeCtl_t, 0, 0, McQueWritePortTypeCtl_network_0_ppPort_f, &value, &mc_que_ptc);
            value = SYS_AT_CHAN_CPUMAC_NETWORK_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, McQueWritePortTypeCtl_t, 0, 0, McQueWritePortTypeCtl_network_1_ppPort_f, &value, &mc_que_ptc);
            value = SYS_AT_CHAN_OAM_START;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, McQueWritePortTypeCtl_t, 0, 0, McQueWritePortTypeCtl_oam_0_ppPort_f, &value, &mc_que_ptc);
            value = SYS_AT_CHAN_OAM_END;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, McQueWritePortTypeCtl_t, 0, 0, McQueWritePortTypeCtl_oam_1_ppPort_f, &value, &mc_que_ptc);
            cmd   = DRV_IOW(McQueWritePortTypeCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &mc_que_ptc));
        }
    }

    return CTC_E_NONE;
}

/*
 * @brief:      DsNetRxBufAdmissionCtl & NetRxBufManagement
 * @notice:     This function is to improving packet drop homogeneity.
 * @detial:     NetRxBufManagement:
 *              TXQMs share one buffer pool. Every TXQM has four level waterlines. If package in 
 *              buffer cross the waterlines, will couse pagckage drop. Only configure low and mid.
 */
int32
_sys_at_datapath_set_dp_netrx_buf(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint8  speed_mode              = 0;
    uint16 mac_client_id           = 0;
    uint16 dp_txqm                 = 0;
    uint16 start_chan              = 0;
    uint16 end_chan                = 0;
    uint16 chan_id                 = 0;
    uint32 val32                   = 0;
    uint32 cmd                     = 0;
    uint32 guarantee_depth         = 0;
    uint32 speed                   = 0;
    uint32 txqm_bw_max             = 1;
    uint32 low_thrd_final          = 0;
    uint32 mid_thrd_final          = 0;
    uint32 step                    = 0;
    uint32 index                   = 0;
    uint32 txqms_bandwith[SYS_AT_TXQM_NUM_PER_DP]     = {0};
    uint32 low_threshold[SYS_AT_TXQM_NUM_PER_DP]      = {0};
    sys_dmps_db_upt_info_t port_info                  = {0};
    NetRxBufManagement_m buf_manage;
    DsNetRxBufAdmissionCtl_m buf_admission_ctl;

    start_chan = core_id * AT_NW_CHAN_NUM_PER_CORE + pp_id * SYS_AT_NW_CHAN_NUM_PER_PP + dp_id * SYS_AT_NW_CHAN_NUM_PER_DP;
    end_chan   = start_chan + SYS_AT_NW_CHAN_NUM_PER_DP;

    /*step 0. calculate all txqms bw (network port) */
    for(dp_txqm = 0; dp_txqm < SYS_AT_TXQM_NUM_PER_DP; dp_txqm++)
    {
        for (chan_id = start_chan; chan_id < end_chan; chan_id++)
        {
            SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN_RX, chan_id));

            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_RX_ID,                 chan_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_RX_SPEED_MODE);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_SPEED_MODE,    speed_mode);

            SYS_CONDITION_CONTINUE(!_sys_at_datapath_is_same_core_pp_dp_txqm(lchip, chan_id, core_id, pp_id, dp_id, dp_txqm, CHAN_DIR_RX));

            SYS_AT_SPEED_MODE_TO_SPEED_VALUE(speed_mode, speed);
            txqms_bandwith[dp_txqm] += speed;
        }
    }

    /*step 1. look up maximum bw*/
    for(dp_txqm = 0; dp_txqm < SYS_AT_TXQM_NUM_PER_DP; dp_txqm++)
    {
        if(txqm_bw_max < txqms_bandwith[dp_txqm])
        {
            txqm_bw_max = txqms_bandwith[dp_txqm];
        }
    }
    SYS_CONDITION_RETURN((0 == txqm_bw_max), CTC_E_NONE);

    for(dp_txqm = 0; dp_txqm < SYS_AT_TXQM_NUM_PER_DP; dp_txqm++)
    {
        for (chan_id = start_chan; chan_id < end_chan; chan_id++)
        {
            SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN_RX, chan_id));

            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_RX_ID,                 chan_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_RX_SPEED_MODE);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_RX_MAC_CLIENT_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_SPEED_MODE,    speed_mode);
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_MAC_CLIENT_ID, mac_client_id);

            SYS_CONDITION_CONTINUE(!_sys_at_datapath_is_same_core_pp_dp_txqm(lchip, chan_id, core_id, pp_id, dp_id, dp_txqm, CHAN_DIR_RX));

            /*step 2. calculate guarantee buffer depth*/
            SYS_AT_SPEED_MODE_TO_SPEED_VALUE(speed_mode, speed);
            guarantee_depth = ((0 == speed) ? 0 : ((speed < 50) ? 5 : (5 * (speed / 50))));
            low_threshold[dp_txqm] += guarantee_depth;

            /*cfg DsNetRxBufAdmissionCtl*/
            index  = DRV_INS(0, mac_client_id);
            val32  = guarantee_depth;
            cmd = DRV_IOR(DsNetRxBufAdmissionCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &buf_admission_ctl));
            DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, DsNetRxBufAdmissionCtl_t, 0, mac_client_id,
                DsNetRxBufAdmissionCtl_cfgGuaranteeBufferNum_f, &val32, &buf_admission_ctl);
            cmd = DRV_IOW(DsNetRxBufAdmissionCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &buf_admission_ctl));
        }

        /*step 3. calculate low/mid threshold*/
        low_thrd_final = low_threshold[dp_txqm] * 5;
        low_thrd_final = (low_thrd_final < 100) ? 100 : low_thrd_final;
        mid_thrd_final = low_threshold[dp_txqm] * 8;
        mid_thrd_final = (mid_thrd_final < 160) ? 160 : mid_thrd_final;
        /* NetRxBufManagement */
        cmd = DRV_IOR(NetRxBufManagement_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, 0, core_id, pp_id, dp_id, cmd, &buf_manage));
        val32 = low_thrd_final;
        step  = NetRxBufManagement_cfgLowThrd1_f - NetRxBufManagement_cfgLowThrd0_f;
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetRxBufManagement_t, 0, 0,
            (NetRxBufManagement_cfgLowThrd0_f + dp_txqm * step), &val32, &buf_manage);
        val32 = mid_thrd_final;
        step  = NetRxBufManagement_cfgMidThrd1_f - NetRxBufManagement_cfgMidThrd0_f;
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetRxBufManagement_t, 0, 0,
            (NetRxBufManagement_cfgMidThrd0_f + dp_txqm * step), &val32, &buf_manage);
        cmd = DRV_IOW(NetRxBufManagement_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, 0, core_id, pp_id, dp_id, cmd, &buf_manage));
    }

    return CTC_E_NONE;
}

#ifdef PCS_ONLY

int32
_sys_at_datapath_nettx_cal(uint8 lchip, uint8 core_id, uint8 pp_id ,uint8 dp_id, uint8 sub_chan_id, uint8 speed_mode, uint8 if_mode)
{
    uint8 cnt       = 0;
    uint8 entry_num = 0;
    uint32 cmd      = 0;
    uint32 index    = 0;
    uint8 chan_to_entry[8] = {0,4,2,6,1,5,3,7};
    uint8 chan_to_cal[8]  = {0,1,2,3,4,5,6,7};

    CTC_ERROR_RETURN(_sys_at_mac_get_cal_by_lane(lchip, sub_chan_id % 8, if_mode, chan_to_cal));

    SYS_AT_GET_SERDES_NUM_BY_MODE(if_mode, entry_num);
#if 0
    if (CTC_PORT_SPEED_200G == speed_mode)
    {
        entry_num = 2;
    }
    else if (CTC_PORT_SPEED_400G == speed_mode)
    {
        entry_num = 4;
    }
    else if (CTC_PORT_SPEED_800G == speed_mode)
    {
        entry_num = 8;
    }
    else
    {
        entry_num = 1;
    }
#endif
    for (cnt = 0; cnt < entry_num; cnt++)
    {
        if ((sub_chan_id % 8 + cnt) >= 8)
        {
            continue;
        }
        index = DRV_INS(0, chan_to_entry[sub_chan_id % 8 + cnt]);
        cmd   = DRV_IOW(NetTxCal_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &(chan_to_cal[sub_chan_id % 8 + cnt])));
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write %-50s dp %-15d offset %-15d  0x%-30X\n", "NetTxCal_t",
            dp_id, chan_to_entry[sub_chan_id % 8 + cnt], chan_to_cal[sub_chan_id % 8 + cnt]); 
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_nettx_memory(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 sub_chan_id, uint8 speed_mode)
{
    CTC_ERROR_RETURN(_sys_at_datapath_set_nettx_credit(lchip, core_id, pp_id, dp_id, sub_chan_id, speed_mode));
    CTC_ERROR_RETURN(_sys_at_datapath_set_nettx_thrd(lchip, core_id, pp_id, dp_id, sub_chan_id, speed_mode));
    CTC_ERROR_RETURN(_sys_at_datapath_set_nettx_timer_thrd(lchip, core_id, pp_id, dp_id, sub_chan_id, speed_mode));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_nettx_cfg(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint16 dport)
{
    uint16 chan_id = 0;
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_dport_relative_id(lchip, dport, DMPS_DB_TYPE_CHAN, &chan_id));

    CTC_ERROR_RETURN(_sys_at_datapath_nettx_cal(lchip, core_id, pp_id, dp_id,
        DMPS_DB_CHAN(chan_id).sub_chan_id, DMPS_DB_CHAN(chan_id).speed_mode, DMPS_DB_PORT(dport).if_mode));

    CTC_ERROR_RETURN(_sys_at_datapath_nettx_memory(lchip, core_id, pp_id, dp_id,
        DMPS_DB_CHAN(chan_id).sub_chan_id, DMPS_DB_CHAN(chan_id).speed_mode));

    return CTC_E_NONE;
}
#endif

int32
_sys_at_nettx_speed_to_credit(uint8 lchip, uint16 speed)
{
    uint16 core_pll = 0;
    uint32 credit   = 0;

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1));

    if (900 == core_pll)
    {
        credit =
            (speed>=400) ? 56  :
            (speed>=200) ? 32  :
            (speed>=100) ? 20  :
            (speed>=40)  ? 12  :
            (speed>=25)  ? 10  :
            (speed>=10)  ? 8   : 0;
    }
    else
    {
        credit =
            (speed>=800) ? 120 :
            (speed>=400) ? 64  :
            (speed>=200) ? 48  :
            (speed>=100) ? 24  :
            (speed>=50)  ? 16  :
            (speed>=40)  ? 16  :
            (speed>=25)  ? 12  :
            (speed>=10)  ? 8   : 0;
    }

    return credit;
}

int32
_sys_at_datapath_set_nettx_credit_thrd(uint8 lchip, sys_dmps_db_chan_info_t* chan_info)
{
    uint8   core_id      = 0;
    uint8   pp_id        = 0;
    uint8   dp_id        = 0;
    uint32  dp_client_id = 0;
    uint32  cmd          = 0;
    uint32  index        = 0;
    uint16  speed        = 0;
    uint32  credit       = 0;
    NetTxCreditThrd_m credit_cfg = {{0}};

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    CTC_PTR_VALID_CHECK(chan_info);
    core_id        = chan_info->core_id;
    pp_id          = chan_info->pp_id;
    dp_id          = chan_info->dp_id;
    dp_client_id   = chan_info->mac_client_id;

    SYS_DATAPATH_SYS_MODE_TO_SPEED(chan_info->speed_mode, speed);

    credit = _sys_at_nettx_speed_to_credit(lchip, speed);

    index = DRV_INS(0, dp_client_id); 

    cmd = DRV_IOR(NetTxCreditThrd_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &credit_cfg));

    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetTxCreditThrd_t, 0, dp_client_id, NetTxCreditThrd_data_f, &credit, &credit_cfg);
    cmd = DRV_IOW(NetTxCreditThrd_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &credit_cfg));

    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

int32
_sys_at_datapath_nettx_timer_en(uint8 lchip, sys_dmps_db_chan_info_t* chan_info, uint8 enable)
{
    uint8  core_id          = 0;
    uint8  pp_id            = 0;
    uint8  dp_id            = 0;
    uint8  dp_txqm_id       = 0;
    uint8  txqm_client_id   = 0;
    uint16 mac_client_id    = 0;
    uint16 speed            = 0;
    uint32 cmd              = 0;
    uint32 field_id         = 0;
    uint32 uc_thrd          = 3;
    uint32 mc_thrd          = 3;
    uint32 uc_timer_thrd    = 0;
    uint32 mc_timer_thrd    = 0;
    uint32 index            = 0;
    uint32 timer_enable     = 0;
    uint32 uc_guar_thrd     = 3;
    uint32 mc_guar_thrd     = 3;
    NetTxTimerEnCtl_m       enable_cfg;
    NetTxUcTxTimerThrdCfg_m uc_tx_timer_thrd;
    NetTxMcTxTimerThrdCfg_m mc_tx_timer_thrd;
    NetTxUcTxThrdCfg_m      uc_tx_thrd;
    NetTxMcTxThrdCfg_m      mc_tx_thrd;

    CTC_PTR_VALID_CHECK(chan_info);
    core_id        = chan_info->core_id;
    pp_id          = chan_info->pp_id;
    dp_id          = chan_info->dp_id;
    dp_txqm_id     = chan_info->txqm_id;
    mac_client_id  = chan_info->mac_client_id;
    txqm_client_id = mac_client_id % SYS_AT_MAC_CLIENT_PER_TXQM;

    SYS_DATAPATH_SYS_MODE_TO_SPEED(chan_info->speed_mode, speed);

    uc_thrd = ((speed > 0) && (speed <= 25)) ? 5 : 3;
    mc_thrd = ((speed > 0) && (speed <= 25)) ? 5 : 3;
    uc_guar_thrd = ((speed > 0) && (speed <= 25)) ? 5 : 3;
    mc_guar_thrd = ((speed > 0) && (speed <= 25)) ? 5 : 3;

    /*1. Timer en*/
    index = DRV_INS(0, 0);
    cmd   = DRV_IOR(NetTxTimerEnCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &enable_cfg));

    field_id = NetTxTimerEnCtl_txTimerEn0_f + (NetTxTimerEnCtl_txTimerEn1_f - NetTxTimerEnCtl_txTimerEn0_f) * dp_txqm_id;
    DRV_IOR_FIELD(lchip, NetTxTimerEnCtl_t, field_id, &timer_enable, &enable_cfg);

    if(enable)
    {
        CTC_BIT_SET(timer_enable, txqm_client_id);
    }
    else
    {
        CTC_BIT_UNSET(timer_enable, txqm_client_id);
    }

    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetTxTimerEnCtl_t, 0, 0, field_id, &timer_enable, &enable_cfg);
    cmd = DRV_IOW(NetTxTimerEnCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &enable_cfg));

    mc_timer_thrd = speed >= 400 ? 28 :
                    speed >= 200 ? 56 :
                    speed >= 100 ? 84 :
                    speed >= 50  ? 170 :
                    speed >= 40  ? 220 :
                    speed >= 25  ? 300 :
                    speed >= 1   ? 300 : 0;
    uc_timer_thrd = mc_timer_thrd;

    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        uc_thrd = 6;
        mc_thrd = 6;
        uc_guar_thrd = 5;
        mc_guar_thrd = 5;
        uc_thrd = ((speed > 0) && (speed <= 25)) ? 7 : 6;
        mc_thrd = ((speed > 0) && (speed <= 25)) ? 7 : 6;
        uc_guar_thrd = ((speed > 0) && (speed <= 25)) ? 6 : 5;
        mc_guar_thrd = ((speed > 0) && (speed <= 25)) ? 6 : 5;
        mc_timer_thrd = speed >= 400 ? 42 :
                        speed >= 200 ? 84 :
                        speed >= 100 ? 166 :
                        speed >= 50  ? 280 :
                        speed >= 40  ? 300 :
                        speed >= 25  ? 300 :
                        speed >= 1   ? 300 : 0;
        uc_timer_thrd = mc_timer_thrd;
    }

    /*2. Timer thrd*/
    /* Uc */
    index = DRV_INS(0, mac_client_id);
    cmd = DRV_IOR(NetTxUcTxTimerThrdCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &uc_tx_timer_thrd));

    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetTxUcTxTimerThrdCfg_t, 0, mac_client_id, NetTxUcTxTimerThrdCfg_ucTxTimerThrd_f,
        &uc_timer_thrd, &uc_tx_timer_thrd);

    cmd = DRV_IOW(NetTxUcTxTimerThrdCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &uc_tx_timer_thrd));

    /* Mc */
    index = DRV_INS(0, mac_client_id);
    cmd = DRV_IOR(NetTxMcTxTimerThrdCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &mc_tx_timer_thrd));

    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetTxMcTxTimerThrdCfg_t, 0, mac_client_id, NetTxMcTxTimerThrdCfg_mcTxTimerThrd_f,
        &mc_timer_thrd, &mc_tx_timer_thrd);

    cmd = DRV_IOW(NetTxMcTxTimerThrdCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &mc_tx_timer_thrd));

    /*3. Tx thrd*/
    /* Uc */
    cmd = DRV_IOR(NetTxUcTxThrdCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &uc_tx_thrd));

    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetTxUcTxThrdCfg_t, 0, mac_client_id, NetTxUcTxThrdCfg_ucTxthrd_f,
        &uc_thrd, &uc_tx_thrd);
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetTxUcTxThrdCfg_t, 0, mac_client_id, NetTxUcTxThrdCfg_ucGuaranteeTxThrd_f,
        &uc_guar_thrd, &uc_tx_thrd);

    cmd = DRV_IOW(NetTxUcTxThrdCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &uc_tx_thrd));

    /* Mc */
    cmd = DRV_IOR(NetTxMcTxThrdCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &mc_tx_thrd));

    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetTxMcTxThrdCfg_t, 0, mac_client_id, NetTxMcTxThrdCfg_mcTxthrd_f,
        &mc_thrd, &mc_tx_thrd);
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetTxMcTxThrdCfg_t, 0, mac_client_id, NetTxMcTxThrdCfg_mcGuaranteeTxThrd_f,
        &mc_guar_thrd, &mc_tx_thrd);

    cmd = DRV_IOW(NetTxMcTxThrdCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &mc_tx_thrd));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_nettx_switch_to_ready(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint32 cmd              = 0;
    uint32 index            = 0;
    uint32 tmp_val32        = 0;
    NetTxMiscCtl_m misc_ctl = {{0}};

    index = DRV_INS(0, 0);
    
    cmd = DRV_IOR(NetTxMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &misc_ctl));
    
    tmp_val32 = 1;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetTxMiscCtl_t, 0, 0, NetTxMiscCtl_netTxReady_f, &tmp_val32, &misc_ctl);
    
    cmd = DRV_IOW(NetTxMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &misc_ctl));

    return CTC_E_NONE;
}


STATIC int32
_sys_at_datapath_nettx_init(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint16 chan_id = 0;
    uint8  port_type  = 0;
    uint16 start_chan = 0;
    uint16 end_chan   = 0;
    sys_dmps_db_chan_info_t chan_info = {0};
    sys_dmps_db_upt_info_t port_info  = {0};

    DP_DEBUG_FUNCTION_CALLED_PRINT();
#ifdef PCS_ONLY
    uint16 dport   = 0;

    CTC_ERROR_RETURN(_sys_at_datapath_nettx_register(lchip, core_id, pp_id, dp_id));

    for (dport = 0; dport < DMPS_MAX_PORT_NUM; dport++)
    {
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport));
        SYS_CONDITION_CONTINUE(SYS_DMPS_NETWORK_PORT != DMPS_DB_PORT(dport).port_type);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_dport_relative_id(lchip, dport, DMPS_DB_TYPE_CHAN, &chan_id));

        if ((core_id == DMPS_DB_CHAN(chan_id).core_id)
            && (pp_id == DMPS_DB_CHAN(chan_id).pp_id)
            && (dp_id == DMPS_DB_CHAN(chan_id).dp_id))
        {
            CTC_ERROR_RETURN(_sys_at_datapath_nettx_cfg(lchip, core_id, pp_id, dp_id, dport));
        }
    }
#else
    start_chan = core_id * AT_NW_CHAN_NUM_PER_CORE + pp_id * SYS_AT_NW_CHAN_NUM_PER_PP + dp_id * SYS_AT_NW_CHAN_NUM_PER_DP;
    end_chan   = start_chan + SYS_AT_NW_CHAN_NUM_PER_DP;

    chan_info.core_id = core_id;
    chan_info.pp_id   = pp_id;
    chan_info.dp_id   = dp_id;

    /* network chan */
    for (chan_id = start_chan; chan_id < end_chan; chan_id++)
    {
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id));
        chan_info.chan_id = chan_id;

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_TXQM_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SUB_CHAN_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SPEED_MODE);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_TXQM_ID,       chan_info.txqm_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID,   chan_info.sub_chan_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID, chan_info.mac_client_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE,    chan_info.speed_mode);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,          port_type);

        SYS_CONDITION_CONTINUE(SYS_DMPS_NETWORK_PORT != port_type);

        CTC_ERROR_RETURN(_sys_at_datapath_set_nettx_credit_thrd(lchip, &chan_info));
        CTC_ERROR_RETURN(_sys_at_datapath_nettx_timer_en(lchip, &chan_info, TRUE));
    }

    CTC_ERROR_RETURN(_sys_at_datapath_nettx_switch_to_ready(lchip, core_id, pp_id, dp_id));

    DP_DEBUG_FUNCTION_RETURN_PRINT();
#endif
    return CTC_E_NONE;
}


#ifdef PCS_ONLY

int32
_sys_at_datapath_netrx_register(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 speed_mode)
{
    uint32 cmd     = 0;
    uint32 value   = 0;
    //uint32 index  = 0;
    NetRxWrrWeight_m netrx_wrr_wei;

    CTC_ERROR_RETURN(_sys_at_datapath_set_dp_netrx_buf(lchip, core_id, pp_id, dp_id));
    /* NetRxWrrWeight */
    cmd = DRV_IOR(NetRxWrrWeight_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, 0, core_id, pp_id, dp_id, cmd, &netrx_wrr_wei));
    SYS_AT_SPEED_MODE_TO_NETRX_WRR_WEI(speed_mode, value);
    //value = 0x1;
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, NetRxWrrWeight_t, 0, NetRxWrrWeight_cfgNetWorkWeight0_f, &value, &netrx_wrr_wei);
    SYS_AT_SPEED_MODE_TO_NETRX_WRR_WEI(speed_mode, value);
    //value = 0x1;
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, NetRxWrrWeight_t, 0, NetRxWrrWeight_cfgNetWorkWeight1_f, &value, &netrx_wrr_wei);
    cmd = DRV_IOW(NetRxWrrWeight_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, 0, core_id, pp_id, dp_id, cmd, &netrx_wrr_wei));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_netrx_port_chan_mapping(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id,
                                                uint8 sub_chan_id, uint8 speed_mode)
{
    uint32 cmd     = 0;
    uint32 index   = 0;
    uint32 value   = 0;
    //DsNetRxPortToChanMap_m port_to_chan;
    //DsNetRxChanToPortMap_m chan_to_port;

    /*port to channel*/
    index = DRV_INS(0, sub_chan_id);
    value = sub_chan_id;
    cmd = DRV_IOW(DsNetRxPortToChanMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &value));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write %-50s dp %-15d offset %-15d  0x%-30X\n", "DsNetRxPortToChanMap_t",
        dp_id, sub_chan_id, value);

    /*channel to port*/
    index = DRV_INS(0, sub_chan_id);
    value = sub_chan_id;
    cmd = DRV_IOW(DsNetRxChanToPortMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &value));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write %-50s dp %-15d offset %-15d  0x%-30X\n", "DsNetRxChanToPortMap_t",
        dp_id, sub_chan_id, value);

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_netrx_ds_chan_mode(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id,
                                            uint8 sub_chan_id, uint8 speed_mode)
{
    uint32 cmd     = 0;
    uint32 index   = 0;
    uint32 value   = 0;

    index = DRV_INS(0, sub_chan_id);
    SYS_AT_SPEED_MODE_TO_NETRX_DS_CHAN_MODE(speed_mode, value);
    cmd = DRV_IOW(DsChannelizeMode_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &value));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write %-50s dp %-15d offset %-15d  0x%-30X\n", "DsChannelizeMode_t",
        dp_id, sub_chan_id, value);

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_netrx_misc_chan_pkt_len_chk(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id,
                                                    uint8 sub_chan_id, uint8 speed_mode)
{
    uint32 cmd     = 0;
    uint32 index   = 0;
    uint32 value   = 0;

    index = DRV_INS(0, sub_chan_id);
    SYS_AT_SPEED_MODE_TO_NETRX_BUF_ADMISS_CTL(speed_mode, value);
    cmd = DRV_IOW(DsNetRxBufAdmissionCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &value));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write %-50s dp %-15d offset %-15d  0x%-30X\n", "DsNetRxBufAdmissionCtl_t",
        dp_id, sub_chan_id, value);

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_netrx_port_wei_cfg(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id,
                                            uint8 sub_chan_id, uint8 speed_mode)
{
    uint32 cmd     = 0;
    uint32 index   = 0;
    uint32 value   = 0;

    index = DRV_INS(0, sub_chan_id);
    SYS_AT_SPEED_MODE_TO_NETRX_PORT_WEI_CFG(speed_mode, value);
    cmd = DRV_IOW(DsNetRxPortWeightCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &value));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write %-50s dp %-15d offset %-15d  0x%-30X\n", "DsNetRxPortWeightCfg_t",
        dp_id, sub_chan_id, value);

    return CTC_E_NONE;
}

int32
_sys_at_datapath_netrx_memory(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 sub_chan_id, uint8 speed_mode)
{
    CTC_ERROR_RETURN(_sys_at_datapath_set_netrx_port_chan_mapping(lchip, core_id, pp_id, dp_id, sub_chan_id, speed_mode));
    CTC_ERROR_RETURN(_sys_at_datapath_set_netrx_ds_chan_mode(lchip, core_id, pp_id, dp_id, sub_chan_id, speed_mode));
    CTC_ERROR_RETURN(_sys_at_datapath_set_netrx_misc_chan_pkt_len_chk(lchip, core_id, pp_id, dp_id, sub_chan_id, speed_mode));
    CTC_ERROR_RETURN(_sys_at_datapath_set_netrx_port_wei_cfg(lchip, core_id, pp_id, dp_id, sub_chan_id, speed_mode));

    return CTC_E_NONE;
}

uint32
_sys_at_datapath_netrx_cfg(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 dport)
{
    uint16 chan_id = 0;

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_dport_relative_id(lchip, dport, DMPS_DB_TYPE_CHAN, &chan_id));

    if (0 == DMPS_DB_CHAN(chan_id).sub_chan_id)
    {
        CTC_ERROR_RETURN(_sys_at_datapath_netrx_register(lchip, core_id, pp_id, dp_id,
            DMPS_DB_CHAN(chan_id).speed_mode));
    }

    CTC_ERROR_RETURN(_sys_at_datapath_netrx_memory(lchip, core_id, pp_id, dp_id,
        DMPS_DB_CHAN(chan_id).sub_chan_id, DMPS_DB_CHAN(chan_id).speed_mode));

    return CTC_E_NONE;
}
#endif

int32
_sys_at_datapath_set_dp_netrx_wrr_weight(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint8   dp_txqm_id     = 0;
    uint8   port_type      = 0;
    uint8   speed_mode     = 0;
    uint8   txqm_id        = 0;
    uint16  mac_client_id  = 0;
    uint16  start_chan     = 0;
    uint16  end_chan       = 0;
    uint16  chan_id        = 0;
    uint16  txqm_client_id = 0;
    uint16  dp_client_id   = 0;
    uint16  weight         = 0;
    uint32  index          = 0;
    uint32  cmd            = 0;
    uint16  divisor        = 0;
    uint32  opt_weight     = 0;
    uint32  step           = NetRxWrrWeight_cfgNetWorkWeight1_f - NetRxWrrWeight_cfgNetWorkWeight0_f;
    uint16  txqm_weight[SYS_AT_TXQM_NUM_PER_DP][SYS_AT_MAC_CLIENT_PER_TXQM] = {{0}};
    uint16  weight_arr[SYS_AT_TXQM_NUM_PER_DP] = {0};
    sys_dmps_db_upt_info_t port_info           = {0};
    NetRxWrrWeight_m       wrr_cfg;
    DsNetRxPortWeightCfg_m port_weight_cfg;

    start_chan = core_id * AT_NW_CHAN_NUM_PER_CORE + pp_id * SYS_AT_NW_CHAN_NUM_PER_PP + dp_id * SYS_AT_NW_CHAN_NUM_PER_DP;
    end_chan   = start_chan + SYS_AT_NW_CHAN_NUM_PER_DP;

    /*1. fill all network port weight in this dp */
    for (chan_id = start_chan; chan_id < end_chan; chan_id++)
    {
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN_RX, chan_id));

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_RX_ID,                 chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_RX_TXQM_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_RX_MAC_CLIENT_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_RX_SPEED_MODE);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,             port_type);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_TXQM_ID,       txqm_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_MAC_CLIENT_ID, mac_client_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_SPEED_MODE,    speed_mode);

        SYS_CONDITION_CONTINUE(SYS_DMPS_NETWORK_PORT != port_type);

        SYS_DATAPATH_SYS_SPEED_TO_WRRCFG(speed_mode, weight);
        dp_txqm_id = txqm_id;

        txqm_client_id = mac_client_id % SYS_AT_MAC_CLIENT_PER_TXQM;
        txqm_weight[dp_txqm_id][txqm_client_id] = weight;
        weight_arr[dp_txqm_id]                 += weight;
    }

    /*2. set NetRxWrrWeight */
    CTC_ERROR_RETURN(sys_usw_datapath_get_gcd(weight_arr, SYS_AT_TXQM_NUM_PER_DP, &divisor));

    index = DRV_INS(0, 0);
    cmd = DRV_IOR(NetRxWrrWeight_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &wrr_cfg));
    for(dp_txqm_id = 0; dp_txqm_id < SYS_AT_TXQM_NUM_PER_DP; dp_txqm_id++)
    {
        opt_weight = weight_arr[dp_txqm_id] / divisor;
        opt_weight = (opt_weight > 31) ? 31 : opt_weight;   /* cfgNetWorkWeight0/1_f has only 5 bit */
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetRxWrrWeight_t, 0, 0,
            (NetRxWrrWeight_cfgNetWorkWeight0_f + step * dp_txqm_id), &opt_weight, &wrr_cfg);
    }
    cmd = DRV_IOW(NetRxWrrWeight_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &wrr_cfg));

    /*3. set DsNetRxPortWeightCfg*/
    for(dp_txqm_id = 0; dp_txqm_id < SYS_AT_TXQM_NUM_PER_DP; dp_txqm_id++)
    {
        CTC_ERROR_RETURN(sys_usw_datapath_get_gcd(txqm_weight[dp_txqm_id], SYS_AT_MAC_CLIENT_PER_TXQM, &divisor));

        for(txqm_client_id = 0; txqm_client_id < SYS_AT_MAC_CLIENT_PER_TXQM; txqm_client_id++)
        {
            dp_client_id = dp_txqm_id * SYS_AT_MAC_CLIENT_PER_TXQM + txqm_client_id;

            index  = DRV_INS(0, dp_client_id);
            cmd = DRV_IOR(DsNetRxPortWeightCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &port_weight_cfg));

            opt_weight = txqm_weight[dp_txqm_id][txqm_client_id] / divisor;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, DsNetRxPortWeightCfg_t, 0, dp_client_id,
                DsNetRxPortWeightCfg_weight_f, &opt_weight, &port_weight_cfg);

            cmd = DRV_IOW(DsNetRxPortWeightCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &port_weight_cfg));
        }
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_at_datapath_netrx_init(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
#ifdef PCS_ONLY
    uint16 chan_id = 0;
    uint16 dport   = 0;

    for (dport = 0; dport < DMPS_MAX_PORT_NUM; dport++)
    {
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport));
        SYS_CONDITION_CONTINUE(SYS_DMPS_NETWORK_PORT != DMPS_DB_PORT(dport).port_type);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_dport_relative_id(lchip, dport, DMPS_DB_TYPE_CHAN_RX, &chan_id));

        if ((core_id == DMPS_DB_CHAN_RX(chan_id).core_id)
            && (pp_id == DMPS_DB_CHAN_RX(chan_id).pp_id)
            && (dp_id == DMPS_DB_CHAN_RX(chan_id).dp_id))
        {
            CTC_ERROR_RETURN(_sys_at_datapath_netrx_cfg(lchip, core_id, pp_id, dp_id, dport));
        }
    }
#else
    CTC_ERROR_RETURN(_sys_at_datapath_set_dp_netrx_wrr_weight(lchip, core_id, pp_id, dp_id));
    CTC_ERROR_RETURN(_sys_at_datapath_set_dp_netrx_buf(lchip, core_id, pp_id, dp_id));
#endif

    return CTC_E_NONE;
}

#ifdef AT_CPUMAC
STATIC int32
_sys_at_datapath_init_sup_cpumac(uint8 lchip, uint8 core_id)
{
    uint32 cmd    = 0;
    uint32 value  = 0;
    uint32 index  = 0;
    CpuMacCtlEnClk_m     cm_en;
    CpuMacCtlResetCtl_m    cpumac_ctl_reset;
    CpuMacHssLaneCfg_m     cpumac_hss_lane;
    CpuMacHssTxCfg_m       cpumac_hss_tx;
    //CpuMacClockTreeCfg_m cpumac_clk_tree_cfg;
    //CpuMacHssQuadCfg_m   hss_q_cfg;
    //CpuMacHssIddqEnable_m hss_iddq_en;

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    /* Enable CpuMac clock */
    cmd = DRV_IOR(CpuMacCtlEnClk_t, DRV_ENTRY_FLAG);
    index = DRV_INS(0, 0);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cm_en));
    value = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkLed_f, &value, &cm_en);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkQuadSgmac_f, &value, &cm_en);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmac0_f, &value, &cm_en);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmac1_f, &value, &cm_en);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmac2_f, &value, &cm_en);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmac3_f, &value, &cm_en);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmiiPcs0_f, &value, &cm_en);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmiiPcs1_f, &value, &cm_en);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmiiPcs2_f, &value, &cm_en);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkSgmiiPcs3_f, &value, &cm_en);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkXfiPcs0_f, &value, &cm_en);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkXfiPcs1_f, &value, &cm_en);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkXfiPcs2_f, &value, &cm_en);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlEnClk_t, 0, CpuMacCtlEnClk_enClkXfiPcs3_f, &value, &cm_en);
    cmd = DRV_IOW(CpuMacCtlEnClk_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cm_en));

    /* Release CpuMacCtlReset */
    index  = DRV_INS(0, 0);
    cmd = DRV_IOR(CpuMacCtlResetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumac_ctl_reset));
    value = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreCmn_f,          &value, &cpumac_ctl_reset);
    value = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreAnethLane0_f,   &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreAnethLane1_f,   &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreAnethLane2_f,   &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreAnethLane3_f,   &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreAnethRegLane0_f,&value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreAnethRegLane1_f,&value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreAnethRegLane2_f,&value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreAnethRegLane3_f,&value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreCgPcs_f,        &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreMii0_f,         &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreMii1_f,         &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreMii2_f,         &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreMii3_f,         &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCorePcs0_f,         &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCorePcs1_f,         &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCorePcs2_f,         &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCorePcs3_f,         &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreQuadSgmacReg_f, &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreQuadSgmac_f,    &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreSgmac0_f,       &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreSgmac1_f,       &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreSgmac2_f,       &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreSgmac3_f,       &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreSharedFecReg_f, &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreSharedMiiReg_f, &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreSharedPcsReg_f, &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreXlgPcs0_f,      &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetCoreXlgPcs1_f,      &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetHssRxLane0_f,       &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetHssRxLane1_f,       &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetHssRxLane2_f,       &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetHssRxLane3_f,       &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetSharedFec_f,        &value, &cpumac_ctl_reset);
    value = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetHssTxLane0_f,       &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetHssTxLane1_f,       &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetHssTxLane2_f,       &value, &cpumac_ctl_reset);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacCtlResetCtl_t, 0, CpuMacCtlResetCtl_resetHssTxLane3_f,       &value, &cpumac_ctl_reset);
    cmd = DRV_IOW(CpuMacCtlResetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumac_ctl_reset));

    index  = DRV_INS(0, 0);
    cmd = DRV_IOR(CpuMacHssLaneCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumac_hss_lane));
    #ifdef EMULATION_ENV
        value = 1;
    #else
        value = 0;
    #endif
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssLaneCfg_t, 0, CpuMacHssLaneCfg_cfgForcePmaReady4PcsEnLane0_f,    &value, &cpumac_hss_lane);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssLaneCfg_t, 0, CpuMacHssLaneCfg_cfgForcePmaReady4PcsEnLane1_f,    &value, &cpumac_hss_lane);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssLaneCfg_t, 0, CpuMacHssLaneCfg_cfgForcePmaReady4PcsEnLane2_f,    &value, &cpumac_hss_lane);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssLaneCfg_t, 0, CpuMacHssLaneCfg_cfgForcePmaReady4PcsEnLane3_f,    &value, &cpumac_hss_lane);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssLaneCfg_t, 0, CpuMacHssLaneCfg_cfgForcePmaReady4PcsValueLane0_f, &value, &cpumac_hss_lane);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssLaneCfg_t, 0, CpuMacHssLaneCfg_cfgForcePmaReady4PcsValueLane1_f, &value, &cpumac_hss_lane);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssLaneCfg_t, 0, CpuMacHssLaneCfg_cfgForcePmaReady4PcsValueLane2_f, &value, &cpumac_hss_lane);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssLaneCfg_t, 0, CpuMacHssLaneCfg_cfgForcePmaReady4PcsValueLane3_f, &value, &cpumac_hss_lane);
    cmd = DRV_IOW(CpuMacHssLaneCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumac_hss_lane));

#if 0
    /* Enable CpuMac clock */
    cmd = DRV_IOR(CpuMacClockTreeCfg_t, DRV_ENTRY_FLAG);
    index = DRV_INS(0, 0);
    value = 0;
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumac_clk_tree_cfg));
    //DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, CpuMacClockTreeCfg_t, 0, CpuMacClockTreeCfg_cfgResetHssL0TxDiv2_f, &value, &cpumac_clk_tree_cfg);
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, CpuMacClockTreeCfg_t, 0, CpuMacClockTreeCfg_cfgResetHssL0TxDiv_f,  &value, &cpumac_clk_tree_cfg);
    //DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, CpuMacClockTreeCfg_t, 0, CpuMacClockTreeCfg_cfgResetHssL1TxDiv2_f, &value, &cpumac_clk_tree_cfg);
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, CpuMacClockTreeCfg_t, 0, CpuMacClockTreeCfg_cfgResetHssL1TxDiv_f,  &value, &cpumac_clk_tree_cfg);
    //DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, CpuMacClockTreeCfg_t, 0, CpuMacClockTreeCfg_cfgResetHssL2TxDiv2_f, &value, &cpumac_clk_tree_cfg);
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, CpuMacClockTreeCfg_t, 0, CpuMacClockTreeCfg_cfgResetHssL2TxDiv_f,  &value, &cpumac_clk_tree_cfg);
    //DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, CpuMacClockTreeCfg_t, 0, CpuMacClockTreeCfg_cfgResetHssL3TxDiv2_f, &value, &cpumac_clk_tree_cfg);
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, CpuMacClockTreeCfg_t, 0, CpuMacClockTreeCfg_cfgResetHssL3TxDiv_f,  &value, &cpumac_clk_tree_cfg);
    cmd = DRV_IOW(CpuMacClockTreeCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumac_clk_tree_cfg));

    /*cpumac CpuMacHssQuadCfg*/       
    cmd = DRV_IOR(CpuMacHssQuadCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &hss_q_cfg));
    value = 0;
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, CpuMacHssQuadCfg_t, 0, CpuMacHssQuadCfg_cfgHssQuadGlueRst_f, &value, &hss_q_cfg);
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, CpuMacHssQuadCfg_t, 0, CpuMacHssQuadCfg_cfgHssQuadRegAccRst_f, &value, &hss_q_cfg);
    value = 1;
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, CpuMacHssQuadCfg_t, 0, CpuMacHssQuadCfg_cfgHssQuad_0_cfgHssApbResetBar_f, &value, &hss_q_cfg);
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, CpuMacHssQuadCfg_t, 0, CpuMacHssQuadCfg_cfgHssQuad_1_cfgHssApbResetBar_f, &value, &hss_q_cfg);
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, CpuMacHssQuadCfg_t, 0, CpuMacHssQuadCfg_cfgHssQuad_2_cfgHssApbResetBar_f, &value, &hss_q_cfg);
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, CpuMacHssQuadCfg_t, 0, CpuMacHssQuadCfg_cfgHssQuad_3_cfgHssApbResetBar_f, &value, &hss_q_cfg);
    cmd = DRV_IOW(CpuMacHssQuadCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &hss_q_cfg));
#endif
    cmd = DRV_IOR(CpuMacHssTxCfg_t, DRV_ENTRY_FLAG);
    index = DRV_INS(0, 0);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumac_hss_tx));
    value = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssTxCfg_t, 0, CpuMacHssTxCfg_cfgHssPmaTxClkDivEnLane0_f, &value, &cpumac_hss_tx);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssTxCfg_t, 0, CpuMacHssTxCfg_cfgHssPmaTxClkDivEnLane1_f, &value, &cpumac_hss_tx);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssTxCfg_t, 0, CpuMacHssTxCfg_cfgHssPmaTxClkDivEnLane2_f, &value, &cpumac_hss_tx);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CpuMacHssTxCfg_t, 0, CpuMacHssTxCfg_cfgHssPmaTxClkDivEnLane3_f, &value, &cpumac_hss_tx);
    cmd = DRV_IOW(CpuMacHssTxCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &cpumac_hss_tx));
    DP_DEBUG_FUNCTION_RETURN_PRINT();
    return CTC_E_NONE;
}
#endif

STATIC int32
_sys_at_datapath_init_sup_per_mac_group(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    uint8  half_id = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    uint32 index   = 0;
#ifdef PCS_ONLY
    uint32 fld_id  = 0;
    uint32 step    = 0;
    SupSelCtcMac_m       sup_sel_ctc_mac;
#endif
    CtcMacCtlEnClk_m     ctc_mac_ctl_enclk;
    McPcs800EnClk_m      mcpcs800_enclk;
    CtcMacCtlReset_m     ctc_mac_ctl_rst;
    McPcs800Reset_m      mcpcs800_rst;
    CtcHsCtlReset_m      ctc_hs_ctl_rst;

    DP_DEBUG_FUNCTION_CALLED_PRINT();

#ifdef PCS_ONLY
    /* MacAgg/MacMux/TxqmMux Register Part */
    cmd = DRV_IOR(SupSelCtcMac_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &sup_sel_ctc_mac));
    step   = SupSelCtcMac_cfgSelCtcMac1_f - SupSelCtcMac_cfgSelCtcMac0_f;
    fld_id = SupSelCtcMac_cfgSelCtcMac0_f + mac_group_id * step;
    value = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, SupSelCtcMac_t, 0, fld_id, &value, &sup_sel_ctc_mac);
    cmd = DRV_IOW(SupSelCtcMac_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &sup_sel_ctc_mac));
#endif

    /* Open clock enable:CtcMacCtlEnClk */
    index  = DRV_INS(mac_group_id, 0);
    cmd = DRV_IOR(CtcMacCtlEnClk_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_mac_ctl_enclk));
    value = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlEnClk_t, mac_group_id, CtcMacCtlEnClk_enClkUart_f, &value, &ctc_mac_ctl_enclk);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlEnClk_t, mac_group_id, CtcMacCtlEnClk_enClkMcuIntf_f, &value, &ctc_mac_ctl_enclk);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlEnClk_t, mac_group_id, CtcMacCtlEnClk_enClkMcu_f, &value, &ctc_mac_ctl_enclk);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlEnClk_t, mac_group_id, CtcMacCtlEnClk_enClkMcMac_f, &value, &ctc_mac_ctl_enclk);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlEnClk_t, mac_group_id, CtcMacCtlEnClk_enClkMcHata_f, &value, &ctc_mac_ctl_enclk);
    cmd = DRV_IOW(CtcMacCtlEnClk_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_mac_ctl_enclk));

    /* CtcMacCtlReset.reset rlm reset */
    index  = DRV_INS(mac_group_id, 0);
    cmd = DRV_IOR(CtcMacCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_mac_ctl_rst));
    value = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcuIntf_f, &value, &ctc_mac_ctl_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcPcs800_f, &value, &ctc_mac_ctl_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcMacReg_f, &value, &ctc_mac_ctl_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcMac_f, &value, &ctc_mac_ctl_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcHataReg_f, &value, &ctc_mac_ctl_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcHata_f, &value, &ctc_mac_ctl_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreTsRcQuad_f, &value, &ctc_mac_ctl_rst);
    cmd = DRV_IOW(CtcMacCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_mac_ctl_rst));

    sal_task_sleep(1);
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "delay 1\n");

    value = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcuIntf_f, &value, &ctc_mac_ctl_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcPcs800_f, &value, &ctc_mac_ctl_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcMacReg_f, &value, &ctc_mac_ctl_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcMac_f, &value, &ctc_mac_ctl_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcHataReg_f, &value, &ctc_mac_ctl_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreMcHata_f, &value, &ctc_mac_ctl_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMacCtlReset_t, mac_group_id, CtcMacCtlReset_resetCoreTsRcQuad_f, &value, &ctc_mac_ctl_rst);
    cmd = DRV_IOW(CtcMacCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_mac_ctl_rst));

    /* Open clock Enable:McPcs800EnClk */
    index  = DRV_INS(mac_group_id, 0);
    cmd = DRV_IOR(McPcs800EnClk_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcpcs800_enclk));
    value = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800EnClk_t, mac_group_id, McPcs800EnClk_enClkMcPcs800_f, &value, &mcpcs800_enclk);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800EnClk_t, mac_group_id, McPcs800EnClk_enClkMcPcs400Core1_f, &value, &mcpcs800_enclk);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800EnClk_t, mac_group_id, McPcs800EnClk_enClkMcPcs400Core0_f, &value, &mcpcs800_enclk);
    value = 3;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800EnClk_t, mac_group_id, McPcs800EnClk_enClkMcFecCore1_f, &value, &mcpcs800_enclk);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800EnClk_t, mac_group_id, McPcs800EnClk_enClkMcFecCore0_f, &value, &mcpcs800_enclk);
    cmd = DRV_IOW(McPcs800EnClk_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcpcs800_enclk));

    index  = DRV_INS(mac_group_id, 0);
    cmd = DRV_IOR(McPcs800Reset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcpcs800_rst));
    value = 0x0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800Reset_t, mac_group_id, McPcs800Reset_cfgSoftResetMcFec0_f,    &value, &mcpcs800_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800Reset_t, mac_group_id, McPcs800Reset_cfgSoftResetMcFec1_f,    &value, &mcpcs800_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800Reset_t, mac_group_id, McPcs800Reset_cfgSoftResetMcFecRx0_f,  &value, &mcpcs800_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800Reset_t, mac_group_id, McPcs800Reset_cfgSoftResetMcFecRx1_f,  &value, &mcpcs800_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800Reset_t, mac_group_id, McPcs800Reset_cfgSoftResetMcFecTx0_f,  &value, &mcpcs800_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800Reset_t, mac_group_id, McPcs800Reset_cfgSoftResetMcFecTx1_f,  &value, &mcpcs800_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800Reset_t, mac_group_id, McPcs800Reset_cfgSoftResetMcPcs0_f,    &value, &mcpcs800_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800Reset_t, mac_group_id, McPcs800Reset_cfgSoftResetMcPcs1_f,    &value, &mcpcs800_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800Reset_t, mac_group_id, McPcs800Reset_cfgSoftResetMcPcsReg0_f, &value, &mcpcs800_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800Reset_t, mac_group_id, McPcs800Reset_cfgSoftResetMcPcsReg1_f, &value, &mcpcs800_rst);
    value = 0xff;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800Reset_t, mac_group_id, McPcs800Reset_cfgSoftResetRxChanBmp_f, &value, &mcpcs800_rst);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McPcs800Reset_t, mac_group_id, McPcs800Reset_cfgSoftResetTxChanBmp_f, &value, &mcpcs800_rst);
    cmd = DRV_IOW(McPcs800Reset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcpcs800_rst));

    for (half_id = 0; half_id < AT_MAC_400_NUM_PER_MCMAC; half_id++)
    {
        index  = DRV_INS(2 * mac_group_id + half_id, 0);
        cmd = DRV_IOR(CtcHsCtlReset_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_hs_ctl_rst));
        value = 0;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
            CtcHsCtlReset_resetCoreLane0_f, &value, &ctc_hs_ctl_rst);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
            CtcHsCtlReset_resetCoreLane1_f, &value, &ctc_hs_ctl_rst);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
            CtcHsCtlReset_resetCoreLane2_f, &value, &ctc_hs_ctl_rst);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
            CtcHsCtlReset_resetCoreLane3_f, &value, &ctc_hs_ctl_rst);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
            CtcHsCtlReset_resetCoreAnethRegLane0_f, &value, &ctc_hs_ctl_rst);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
            CtcHsCtlReset_resetCoreAnethRegLane1_f, &value, &ctc_hs_ctl_rst);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
            CtcHsCtlReset_resetCoreAnethRegLane2_f, &value, &ctc_hs_ctl_rst);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
            CtcHsCtlReset_resetCoreAnethRegLane3_f, &value, &ctc_hs_ctl_rst);
        cmd = DRV_IOW(CtcHsCtlReset_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_hs_ctl_rst));
    }

#ifdef PCS_ONLY
    for (half_id = 0; half_id < AT_MAC_400_NUM_PER_MCMAC; half_id++)
    {
        index  = DRV_INS(2 * mac_group_id + half_id, 0);
        cmd = DRV_IOR(CtcHsCtlReset_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_hs_ctl_rst));
        value = 0;
        if ((0 != mac_group_id) && (1 != mac_group_id))
        {
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
                CtcHsCtlReset_resetCoreAnethLane0_f,  &value, &ctc_hs_ctl_rst);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
                CtcHsCtlReset_resetCoreAnethLane1_f,  &value, &ctc_hs_ctl_rst);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
                CtcHsCtlReset_resetCoreAnethLane2_f,  &value, &ctc_hs_ctl_rst);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
                CtcHsCtlReset_resetCoreAnethLane3_f,  &value, &ctc_hs_ctl_rst);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
                CtcHsCtlReset_resetCoreMcPcs400Pma_f, &value, &ctc_hs_ctl_rst);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
                CtcHsCtlReset_resetCoreCmn_f, &value, &ctc_hs_ctl_rst);
        }
        cmd = DRV_IOW(CtcHsCtlReset_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_hs_ctl_rst));
    }
#else
    for (half_id = 0; half_id < AT_MAC_400_NUM_PER_MCMAC; half_id++)
    {
        index  = DRV_INS(2 * mac_group_id + half_id, 0);
        cmd = DRV_IOR(CtcHsCtlReset_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_hs_ctl_rst));
        value = 0;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
            CtcHsCtlReset_resetCoreCmn_f, &value, &ctc_hs_ctl_rst);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcHsCtlReset_t, 2 * mac_group_id + half_id,
            CtcHsCtlReset_resetCoreMcPcs400Pma_f, &value, &ctc_hs_ctl_rst);
        cmd = DRV_IOW(CtcHsCtlReset_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &ctc_hs_ctl_rst));
    }
#endif
    
    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}


STATIC int32
_sys_at_datapath_init_sup_per_dp(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint32 cmd     = 0;
    CtcDpRxCtlReset_m    dp_rxrst;
    CtcDpTxCtlReset_m    dp_txrst;
    
    DP_DEBUG_FUNCTION_CALLED_PRINT();

    sal_memset(&dp_rxrst, 0, sizeof(CtcDpRxCtlReset_m));
    cmd = DRV_IOW(CtcDpRxCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, 0, core_id, pp_id, dp_id, cmd, &dp_rxrst));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcDpRxCtlReset    0 offset 0  0x0 core %u pp %u dp %u\n", core_id, pp_id, dp_id);

    sal_memset(&dp_txrst, 0, sizeof(CtcDpTxCtlReset_m));
    cmd = DRV_IOW(CtcDpTxCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, 0, core_id, pp_id, dp_id, cmd, &dp_txrst));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcDpTxCtlReset    0 offset 0  0x0 core %u pp %u dp %u\n", core_id, pp_id, dp_id);

    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

STATIC int32
_sys_at_datapath_init_sup_per_pp(uint8 lchip, uint8 core_id, uint8 pp_id)
{
    uint8  dp_id                   = 0;
    uint32 index                   = 0;
    uint32 cmd                     = 0;
    CtcBufStoreErmSliceCtlReset_m  bs_erm_rst;
    CtcBufStoreSliceQuadCtlReset_m bs_qud_rst;
    CtcQMgrDeqTopReset_m           qmgr_rst;
    CtcIpeTxCtlReset_m             ipe_tx_rst;
    CtcIpeRxCtlReset_m             ipe_rx_rst;
    CtcIpeAclCtlReset_m            ipeacl_rst;
    CtcEpeRxCtlReset_m             epe_rx_rst;
    CtcEpeTxCtlReset_m             epe_tx_rst;
    CtcAdEditCtlReset_m            ad_ctl_rst;
    CtcKeyCtlReset_m               keyctl_rst;
    
    DP_DEBUG_FUNCTION_CALLED_PRINT();

    /* local core */
    /*CtcBufStoreErmSliceCtlReset*/
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcBufStoreErmSliceCtlReset  0 offset 0  0x0 core %u pp %u dp %u\n", core_id, pp_id, 0xff);
    index = DRV_INS(0, 0);
    sal_memset(&bs_erm_rst, 0, sizeof(CtcBufStoreErmSliceCtlReset_m));
    cmd   = DRV_IOW(CtcBufStoreErmSliceCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &bs_erm_rst));

    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        /* remote core */
        /*CtcBufStoreErmSliceCtlReset*/
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcBufStoreErmSliceCtlReset  0 offset 0  0x0 core %u pp %u dp %u\n", ((0 == core_id) ? 1 : 0), pp_id, 0xff);
        index = DRV_INS(1, 0);
        sal_memset(&bs_erm_rst, 0, sizeof(CtcBufStoreErmSliceCtlReset_m));
        cmd   = DRV_IOW(CtcBufStoreErmSliceCtlReset_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, ((0 == core_id) ? 1 : 0), pp_id, cmd, &bs_erm_rst));
    }

    /*CtcBufStoreSliceQuadCtlReset*/
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcBufStoreSliceQuadCtlReset  0 offset 0  0x0 core %u pp %u dp %u\n", core_id, pp_id, 0xff);
    sal_memset(&bs_qud_rst, 0, sizeof(CtcBufStoreSliceQuadCtlReset_m));
    cmd   = DRV_IOW(CtcBufStoreSliceQuadCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, 0, core_id, pp_id, cmd, &bs_qud_rst));

    /*CtcQMgrDeqTopReset*/
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcQMgrDeqTopReset  0 offset 0  0x0 core %u pp %u dp %u\n", core_id, pp_id, 0xff);
    sal_memset(&qmgr_rst, 0, sizeof(CtcQMgrDeqTopReset_m));
    cmd   = DRV_IOW(CtcQMgrDeqTopReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, 0, core_id, pp_id, cmd, &qmgr_rst));

    /*CtcIpeTxCtlReset*/
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcIpeTxCtlReset  0 offset 0  0x0 core %u pp %u dp %u\n", core_id, pp_id, 0xff);
    sal_memset(&ipe_tx_rst, 0, sizeof(CtcIpeTxCtlReset_m));
    cmd   = DRV_IOW(CtcIpeTxCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, 0, core_id, pp_id, cmd, &ipe_tx_rst));

    /*CtcIpeRxCtlReset*/
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcIpeRxCtlReset  0 offset 0  0x0 core %u pp %u dp %u\n", core_id, pp_id, 0xff);
    sal_memset(&ipe_rx_rst, 0, sizeof(CtcIpeRxCtlReset_m));
    cmd   = DRV_IOW(CtcIpeRxCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, 0, core_id, pp_id, cmd, &ipe_rx_rst));

    /*CtcIpeAclCtlReset*/
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcIpeAclCtlReset  0 offset 0  0x0 core %u pp %u dp %u\n", core_id, pp_id, 0xff);
    sal_memset(&ipeacl_rst, 0, sizeof(CtcIpeAclCtlReset_m));
    cmd   = DRV_IOW(CtcIpeAclCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, 0, core_id, pp_id, cmd, &ipeacl_rst));

    /*CtcEpeRxCtlReset*/
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcEpeRxCtlReset  0 offset 0  0x0 core %u pp %u dp %u\n", core_id, pp_id, 0xff);
    sal_memset(&epe_rx_rst, 0, sizeof(CtcEpeRxCtlReset_m));
    cmd   = DRV_IOW(CtcEpeRxCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, 0, core_id, pp_id, cmd, &epe_rx_rst));

    /*CtcEpeTxCtlReset*/
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcEpeTxCtlReset  0 offset 0  0x0 core %u pp %u dp %u\n", core_id, pp_id, 0xff);
    sal_memset(&epe_tx_rst, 0, sizeof(CtcEpeTxCtlReset_m));
    cmd   = DRV_IOW(CtcEpeTxCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, 0, core_id, pp_id, cmd, &epe_tx_rst));

    /*CtcAdEditCtlReset*/
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcAdEditCtlReset  0 offset 0  0x0 core %u pp %u dp %u\n", core_id, pp_id, 0xff);
    sal_memset(&ad_ctl_rst, 0, sizeof(CtcAdEditCtlReset_m));
    cmd   = DRV_IOW(CtcAdEditCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, 0, core_id, pp_id, cmd, &ad_ctl_rst));

    /*CtcKeyCtlReset*/
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcKeyCtlReset  0 offset 0  0x0 core %u pp %u dp %u\n", core_id, pp_id, 0xff);
    sal_memset(&keyctl_rst, 0, sizeof(CtcKeyCtlReset_m));
    cmd   = DRV_IOW(CtcKeyCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, 0, core_id, pp_id, cmd, &keyctl_rst));

    for (dp_id = 0; dp_id < AT_DP_NUM_PER_PP; dp_id++)
    {
        CTC_ERROR_RETURN(_sys_at_datapath_init_sup_per_dp(lchip, core_id, pp_id, dp_id));
    }
    
    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}



STATIC int32
_sys_at_datapath_init_sup_per_core(uint8 lchip, uint8 core_id)
{
    uint8  pp_id        = 0;
    uint8  mac_group_id = 0;
    uint8 chip_type     = SYS_AT_GET_CHIP_TYPE(lchip);
    uint32 cmd          = 0;
    uint32 value        = 0;
    uint32 index        = 0;
    uint32 sup_rst[4];
    uint32 sup_rst_serdes[4];
    DecodeBmpMask_m              dcd_bmp_mask;
    SupRegCtl_m                  sup_reg;
    SupResetCtl_m                sup_rst_ctl;
    PcieResetCtl_m               pcie_rst;
    SupEnClk_m                   sup_enclk;
    CtcBufStoreProcTopCtlReset_m bs_top_rst;
    CtcPostBrSubCtlReset_m       postbr_rst;
    CtcPreBrCtlReset_m           pre_br_rst;
    CtcMetSliceQuadCtlCtlReset_m met_rst;
    CtcMetMsgCtlReset_m          metmsg_rst;
    CtcQMgrCtlReset_m            qmgr_rst;
    CtcMiscCtlReset_m            misc_rst;
    MacAggCtlReset_m             macagg_rst;
    SupResetSerdesCtl_m          sup_rst_serdes_ctl;
    EcpuDmaResetCtl_m            ecpu_dma_rest;
    Ecpu00ResetCtl_m             ecpu_reset;

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    /* do ecpu reset and ecpu dma reset */
    sal_memset(&ecpu_dma_rest, 0 , sizeof(EcpuDmaResetCtl_m));
    sal_memset(&ecpu_reset, 0 , sizeof(Ecpu00ResetCtl_m));
    if (!sys_usw_chip_get_reset_hw_en(lchip))
    {
        value = 1;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, Ecpu00ResetCtl_t, 0, Ecpu00ResetCtl_cfgEcpuCoreReset_f, &value, &ecpu_reset);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, Ecpu00ResetCtl_t, 0, Ecpu00ResetCtl_cfgEcpuIntfReset_f, &value, &ecpu_reset);
        cmd = DRV_IOW(Ecpu00ResetCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ecpu_reset));
        cmd = DRV_IOW(Ecpu01ResetCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ecpu_reset));
        cmd = DRV_IOW(Ecpu10ResetCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ecpu_reset));
        cmd = DRV_IOW(Ecpu11ResetCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &ecpu_reset));
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, EcpuDmaResetCtl_t, 0, EcpuDmaResetCtl_cfgEcpu0DmaReset_f, &value, &ecpu_dma_rest);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, EcpuDmaResetCtl_t, 0, EcpuDmaResetCtl_cfgEcpu1DmaReset_f, &value, &ecpu_dma_rest);
        cmd = DRV_IOW(EcpuDmaResetCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &pcie_rst));
    }

    /* do PcieResetCtl_cfgSwitchReset reset */
    cmd = DRV_IOR(PcieResetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &pcie_rst));
    value = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, PcieResetCtl_t, 0, PcieResetCtl_cfgSwitchReset_f, &value, &pcie_rst);
    cmd = DRV_IOW(PcieResetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &pcie_rst));

#if defined(EMULATION_ENV) && (PCS_ONLY == 0) && (EMULATOR_ENV == 0)
    /* 1pp/2pp emulation */
    value = 0x273;
    CTC_ERROR_RETURN(drv_usw_chip_write(lchip, ((uint64) 0x40 << 32) |  0x00000180, value));
    value = 0x073;
    CTC_ERROR_RETURN(drv_usw_chip_write(lchip, ((uint64) 0x40 << 32) |  0x00000180, value));
    value = 0xffffffff;
    CTC_ERROR_RETURN(drv_usw_chip_write(lchip, ((uint64) 0x40 << 32) |  0x00000024, value));
#endif

    /* PcieReg.txt */
    cmd = DRV_IOR(SupRegCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &sup_reg));
    value = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, SupRegCtl_t, 0, SupRegCtl_regReqCrossEn_f, &value, &sup_reg);
#if defined(EMULATION_ENV) && (PCS_ONLY == 0) && (EMULATOR_ENV == 0)
    /* 1pp/2pp emulation */
#else
    /* uml/emulator/board/pcs_only emulation */
    value = 0x400;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, SupRegCtl_t, 0, SupRegCtl_regProcTimer_f, &value, &sup_reg);
#endif
    cmd = DRV_IOW(SupRegCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &sup_reg));

    /* do SupResetCtl reset */
    sup_rst[0] = 0xffffffff;
    sup_rst[1] = 0xffffffff;
    sup_rst[2] = 0xffffffff;
    sup_rst[3] = 0xffffffff;
    cmd = DRV_IOW(SupResetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &sup_rst));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write %-80s %-30s\n", "SupResetCtl_t", "0xffffffff ffffffff ffffffff ffffffff");

    sup_rst[0] = 0;
    sup_rst[1] = 0;
    sup_rst[2] = 0;
    sup_rst[3] = 0;
    cmd = DRV_IOW(SupResetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &sup_rst));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write %-80s %-30s\n", "SupResetCtl_t", "0x0");

    /* do SupResetSerdesCtl reset */
    sup_rst_serdes[0] = 0xffffffff;
    sup_rst_serdes[1] = 0xffffffff;
    cmd = DRV_IOW(SupResetSerdesCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &sup_rst_serdes));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write %-80s %-30s\n", "SupResetSerdesCtl_t", "0x0");
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write %-80s %-30s\n", "SupResetSerdesCtl_t", "0xffffffff ffffffff");
    if (SYS_AT_IS_1PP(chip_type))
    {
        sup_rst_serdes[0] = 0;
        sup_rst_serdes[1] = 0;
        cmd = DRV_IOW(SupResetSerdesCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &sup_rst_serdes));
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write %-80s %-30s\n", "SupResetSerdesCtl_t", "0x0");
    }

    /* Open clock enable:SupEnClk */
    cmd = DRV_IOR(SupEnClk_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &sup_enclk));
    value = 0xffffffff;
    cmd = DRV_IOW(SupEnClk_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &value));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write %-80s %-30s\n", "SupEnClk_t", "0xffffffff");

    if (0 == core_id)
    {
        /* DecodeBmpMask */
        cmd = DRV_IOR(DecodeBmpMask_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &dcd_bmp_mask));
        DRV_IOR_FIELD(lchip, DecodeBmpMask_t, DecodeBmpMask_cfgCoreMask_f, &value, &dcd_bmp_mask);
        value = (SYS_AT_CHIP_IS_DC(lchip)) ? 0 : 0x2;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, DecodeBmpMask_t, 0, DecodeBmpMask_cfgCoreMask_f, &value, &dcd_bmp_mask);
        DRV_IOR_FIELD(lchip, DecodeBmpMask_t, DecodeBmpMask_cfgSliceMask_f, &value, &dcd_bmp_mask);
        value = 0xf;
        for (pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));
            CTC_BIT_UNSET(value, pp_id);
        }
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, DecodeBmpMask_t, 0, DecodeBmpMask_cfgSliceMask_f, &value, &dcd_bmp_mask);
        cmd = DRV_IOW(DecodeBmpMask_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &dcd_bmp_mask));
    }

    /* supresetctl_cfgResetCpuMap */
    cmd = DRV_IOR(SupResetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &sup_rst_ctl));
    value = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, SupResetCtl_t, 0, SupResetCtl_cfgResetCpuMap_f, &value, &sup_rst_ctl);
    cmd = DRV_IOW(SupResetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &sup_rst_ctl));
    value = 0;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, SupResetCtl_t, 0, SupResetCtl_cfgResetCpuMap_f, &value, &sup_rst_ctl);
    cmd = DRV_IOW(SupResetCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &sup_rst_ctl));

    /*CtcBufStoreProcTopCtlReset*/
    sal_memset(&bs_top_rst, 0, sizeof(CtcBufStoreProcTopCtlReset_m));
    cmd = DRV_IOW(CtcBufStoreProcTopCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &bs_top_rst));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcBufStoreProcTopCtlReset   0 offset 0  0x0 core %u pp %u dp %u\n", core_id, 0xff, 0xff);

    /*CtcPostBrSubCtlReset*/
    sal_memset(&postbr_rst, 0, sizeof(CtcPostBrSubCtlReset_m));
    cmd = DRV_IOW(CtcPostBrSubCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &postbr_rst));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcPostBrSubCtlReset         0 offset 0  0x0 core %u pp %u dp %u\n", core_id, 0xff, 0xff);

    /*CtcPostBrSubCtlReset*/
    index = DRV_INS(1, 0);
    sal_memset(&postbr_rst, 0, sizeof(CtcPostBrSubCtlReset_m));
    cmd = DRV_IOW(CtcPostBrSubCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &postbr_rst));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcPostBrSubCtlReset         0 offset 0  0x0 core %u pp %u dp %u\n", core_id, 0xff, 0xff);

    /*CtcPreBrCtlReset*/
    sal_memset(&pre_br_rst, 0, sizeof(CtcPreBrCtlReset_m));
    cmd = DRV_IOW(CtcPreBrCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &pre_br_rst));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcPreBrCtlReset         0 offset 0  0x0 core %u pp %u dp %u\n", core_id, 0xff, 0xff);

    /*CtcMetSliceQuadCtlCtlReset*/
    sal_memset(&met_rst, 0, sizeof(CtcMetSliceQuadCtlCtlReset_m));
    cmd = DRV_IOW(CtcMetSliceQuadCtlCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &met_rst));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcMetSliceQuadCtlCtlReset    0 offset 0  0x0 core %u pp %u dp %u\n", core_id, 0xff, 0xff);

    /*CtcMetMsgCtlReset*/
    sal_memset(&metmsg_rst, 0, sizeof(CtcMetMsgCtlReset_m));
    cmd = DRV_IOW(CtcMetMsgCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &metmsg_rst));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcMetMsgCtlReset             0 offset 0  0x0 core %u pp %u dp %u\n", core_id, 0xff, 0xff);

    /*CtcQMgrCtlReset*/
    sal_memset(&qmgr_rst, 0, sizeof(CtcQMgrCtlReset_m));
    cmd = DRV_IOW(CtcQMgrCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &qmgr_rst));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcQMgrCtlReset             0 offset 0  0x0 core %u pp %u dp %u\n", core_id, 0xff, 0xff);

    /*CtcMiscCtlReset*/
    sal_memset(&misc_rst, 0, sizeof(CtcMiscCtlReset_m));
    value = 1;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, CtcMiscCtlReset_t, 0, CtcMiscCtlReset_resetCoreMcu_f, &value, &misc_rst);
    cmd = DRV_IOW(CtcMiscCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &misc_rst));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg CtcMiscCtlReset             0 offset 0  0x0 core %u pp %u dp %u\n", core_id, 0xff, 0xff);

    /*MacAggCtlReset.0*/
    index = DRV_INS(0, 0);
    sal_memset(&macagg_rst, 0, sizeof(MacAggCtlReset_m));
    cmd = DRV_IOW(MacAggCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &macagg_rst));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg MacAggCtlReset             0 offset 0  0x0 core %u pp %u dp %u\n", core_id, 0xff, 0xff);

    /*MacAggCtlReset.1*/
    index = DRV_INS(1, 0);
    sal_memset(&macagg_rst, 0, sizeof(MacAggCtlReset_m));
    cmd = DRV_IOW(MacAggCtlReset_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &macagg_rst));
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "write chip 0 tbl-reg MacAggCtlReset             0 offset 0  0x0 core %u pp %u dp %u\n", core_id, 0xff, 0xff);

    /* TBD: consider if some mac groups are not used */
    for (mac_group_id = 0; mac_group_id < AT_MCMAC_NUM_PER_CORE; mac_group_id++)
    {
        SYS_CONDITION_CONTINUE(!SYS_AT_MAC_GROUP_IS_VAILD(lchip, core_id, mac_group_id));

        if (!SYS_AT_IS_1PP(chip_type))
        {
            /* SupResetSerdesCtl_cfgResetSlice0...3CtcHs0...9 */
            cmd = DRV_IOR(SupResetSerdesCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &sup_rst_serdes_ctl));
            value = 0;
            if (mac_group_id < 10)
            {
                DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, SupResetSerdesCtl_t, 0,
                    SupResetSerdesCtl_cfgResetSlice0CtcHs0_f + 2 * mac_group_id, &value, &sup_rst_serdes_ctl);
                DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, SupResetSerdesCtl_t, 0,
                    SupResetSerdesCtl_cfgResetSlice0CtcHs1_f + 2 * mac_group_id, &value, &sup_rst_serdes_ctl);
            }
            else if (mac_group_id < 15)
            {
                DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, SupResetSerdesCtl_t, 0,
                    SupResetSerdesCtl_cfgResetSlice2CtcHs9_f - 2 * (mac_group_id % 5), &value, &sup_rst_serdes_ctl);
                DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, SupResetSerdesCtl_t, 0,
                    SupResetSerdesCtl_cfgResetSlice2CtcHs8_f - 2 * (mac_group_id % 5), &value, &sup_rst_serdes_ctl);
            }
            else
            {
                DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, SupResetSerdesCtl_t, 0,
                    SupResetSerdesCtl_cfgResetSlice3CtcHs9_f - 2 * (mac_group_id % 5), &value, &sup_rst_serdes_ctl);
                DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, SupResetSerdesCtl_t, 0,
                    SupResetSerdesCtl_cfgResetSlice3CtcHs8_f - 2 * (mac_group_id % 5), &value, &sup_rst_serdes_ctl);
            }
            cmd = DRV_IOW(SupResetSerdesCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &sup_rst_serdes_ctl));
        }

        CTC_ERROR_RETURN(_sys_at_datapath_init_sup_per_mac_group(lchip, core_id, mac_group_id));
    }
#ifdef AT_CPUMAC
    CTC_ERROR_RETURN(_sys_at_datapath_init_sup_cpumac(lchip, core_id));
#endif
    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

STATIC int32
_sys_at_datapath_init_sup(uint8 lchip)
{
    uint8 pp_id     = 0;
    uint8 core_id   = 0;
    uint8 core_num  = 0;

    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "### %s enter\n", __FUNCTION__);
    DP_DEBUG_FUNCTION_CALLED_PRINT();

    core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

    for (core_id = 0; core_id < core_num; core_id++)
    {
        CTC_ERROR_RETURN(_sys_at_datapath_init_sup_per_core(lchip, core_id));
    }

    for (core_id = 0; core_id < core_num; core_id++)
    {
        for (pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));
            CTC_ERROR_RETURN(_sys_at_datapath_init_sup_per_pp(lchip, core_id, pp_id));
        }
    }

#ifdef  EMULATION_ENV
    sal_task_sleep(100);
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "delay 100\n");
#else
    sal_task_sleep(1);
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "delay 1\n");
#endif


    DP_DEBUG_FUNCTION_RETURN_PRINT();

    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "### %s end\n", __FUNCTION__);

    return CTC_E_NONE;
}

int32
_sys_at_datapath_write_dp_table_field(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint32 tbl_id, uint32 fld_id, 
                                      uint8 inst_id, uint32 value, void* tbl_str)
{
    uint32 index = DRV_INS(inst_id, 0);
    uint32 cmd   = 0;

    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, tbl_str));
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, tbl_id, inst_id, fld_id, &value, tbl_str);
    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, tbl_str));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_read_dp_table_field(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint32 tbl_id, uint32 fld_id, 
                                     uint8 inst_id, uint32* p_value, void* tbl_str)
{
    uint32 index = DRV_INS(inst_id, 0);
    uint32 cmd   = 0;

    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, tbl_str));
    DRV_IOR_FIELD(lchip, tbl_id, fld_id, p_value, tbl_str);

    return CTC_E_NONE;
}

int32
_sys_at_datapath_write_pp_table_field(uint8 lchip, uint8 core_id, uint8 pp_id, uint32 tbl_id, uint32 fld_id, 
                                      uint8 inst_id, uint32 value, void* tbl_str)
{
    uint32 cmd   = 0;
    uint32 index = DRV_INS(inst_id, 0);

    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, tbl_str));
    DRV_IOW_FIELD_NZ(core_id, pp_id, 0xff, lchip, tbl_id, inst_id, fld_id, &value, tbl_str);
    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, tbl_str));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_read_pp_table_field(uint8 lchip, uint8 core_id, uint8 pp_id, uint32 tbl_id, uint32 fld_id, 
                                     uint8 inst_id, uint32* p_value, void* tbl_str)
{
    uint32 cmd = 0;
    uint32 index = DRV_INS(inst_id, 0);

    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, tbl_str));
    DRV_IOR_FIELD(lchip, tbl_id, fld_id, p_value, tbl_str);

    return CTC_E_NONE;
}

int32
_sys_at_datapath_write_core_table_field(uint8 lchip, uint8 core_id, uint32 tbl_id, uint32 fld_id,
                                            uint32 inst_id, uint32 value, void* tbl_str)
{
    uint32 index = DRV_INS(inst_id, 0);
    uint32   cmd = 0;

    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, tbl_str));
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, tbl_str);
    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, tbl_str));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_read_core_table_field(uint8 lchip, uint8 core_id, uint32 tbl_id, uint32 fld_id,
                                            uint32 inst_id, uint32* p_value, void* tbl_str)
{
    uint32 cmd = 0;
    uint32 index = DRV_INS(inst_id, 0);

    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, tbl_str));
    DRV_IOR_FIELD(lchip, tbl_id, fld_id, p_value, tbl_str);

    return CTC_E_NONE;
}

#if (SDB_MEM_MODEL != SDB_MODE)
#ifdef AT_CPUMAC
STATIC int32
_sys_at_datapath_init_module_cpumac(uint8 lchip, uint8 core_id)
{
    uint32 cmd   = 0;
    uint32 value = 1;
    uint32 index = 0;
    QuadSgmacInit_m     quad_sgmac_init;
    McuIntfInit_m       mcu_intf_init;

    cmd    = DRV_IOR(QuadSgmacInit_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &quad_sgmac_init));
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, QuadSgmacInit_t, 0, QuadSgmacInit_init_f, &value, &quad_sgmac_init);
    cmd    = DRV_IOW(QuadSgmacInit_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &quad_sgmac_init));

    index  = DRV_INS(AT_MCU_NUM_PER_CORE - 1, 0);
    cmd    = DRV_IOR(McuIntfInit_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcu_intf_init));
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, McuIntfInit_t, AT_MCU_NUM_PER_CORE - 1, McuIntfInit_init_f, &value, &mcu_intf_init);
    cmd    = DRV_IOW(McuIntfInit_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcu_intf_init));

    return CTC_E_NONE;
}

STATIC int32
_sys_at_datapath_init_module_cpumac_check(uint8 lchip, uint8 core_id)
{
    uint32 cmd   = 0;
    uint32 value = 1;
    uint32 index = 0;
    QuadSgmacInitDone_m quad_sgmac_init_done;
    McuIntfInitDone_m    mcu_intf_init_done;

    cmd    = DRV_IOR(QuadSgmacInitDone_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &quad_sgmac_init_done));
    DRV_IOR_FIELD(lchip, QuadSgmacInitDone_t, QuadSgmacInitDone_initDone_f, &value, &quad_sgmac_init_done);
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QuadSgmacInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    index  = DRV_INS(AT_MCU_NUM_PER_CORE - 1, 0);
    cmd    = DRV_IOR(McuIntfInitDone_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcu_intf_init_done));
    DRV_IOR_FIELD(lchip, McuIntfInitDone_t, McuIntfInitDone_initDone_f, &value, &mcu_intf_init_done);
    if (0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [McuIntfInit.%d] Feature not initialized \n", AT_MCU_NUM_PER_CORE - 1);
        return CTC_E_NOT_INIT;
    }

    return CTC_E_NONE;
}
#endif

STATIC int32
_sys_at_datapath_init_module_per_mac_group(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    uint32 cmd    = 0;
    uint32 value  = 1;
    uint32 index  = 0;
    uint32 tbl_id = 0;
    McMacInit_m          mac_init;
    McMacStatsInit_m     mac_stats_init;
#ifndef EMULATOR_ENV
    uint8 chip_type = SYS_AT_GET_CHIP_TYPE(lchip);
    McuIntfInit_m        mcu_intf_init;
#endif
    index  = DRV_INS(mac_group_id, 0);

    tbl_id = McMacInit_t;
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_init));
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, McMacInit_init_f, &value, &mac_init);
    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_init));

    tbl_id = McMacStatsInit_t;
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_stats_init));
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, McMacStatsInit_quadSgmac0Init_f, &value, &mac_stats_init);
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, McMacStatsInit_quadSgmac1Init_f, &value, &mac_stats_init);
    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_stats_init));

#ifndef EMULATOR_ENV
    if (!((SYS_AT_IS_1PP(chip_type)) && ((18 == mac_group_id) || (19 == mac_group_id))))
    {
        tbl_id = McuIntfInit_t;
        cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcu_intf_init));
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, mac_group_id, McuIntfInit_init_f, &value, &mcu_intf_init);
        cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcu_intf_init));
    }
#endif

    return CTC_E_NONE;
}

STATIC int32
_sys_at_datapath_init_module_per_mac_group_check(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    uint32 cmd    = 0;
    uint32 value  = 0;
    uint32 index  = 0;
    uint32 tbl_id = 0;
    McMacInitDone_m      mac_init_done;
    McMacStatsInitDone_m mac_stats_init_done;
#ifndef EMULATOR_ENV
    uint8 chip_type = SYS_AT_GET_CHIP_TYPE(lchip);
    McuIntfInitDone_m    mcu_intf_init_done;
#endif
    index  = DRV_INS(mac_group_id, 0);

    tbl_id = McMacInitDone_t;
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_init_done));
    DRV_IOR_FIELD(lchip, tbl_id, McMacInitDone_initDone_f, &value, &mac_init_done);
    if (0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [McMacInit.%d] Feature not initialized \n", mac_group_id);
        return CTC_E_NOT_INIT;
    }

    tbl_id = McMacStatsInitDone_t;
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_stats_init_done));
    DRV_IOR_FIELD(lchip, tbl_id, McMacStatsInitDone_quadSgmac0InitDone_f, &value, &mac_stats_init_done);
    if (0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [McMacStatsInit0.%d] Feature not initialized \n", mac_group_id);
        return CTC_E_NOT_INIT;
    }

    tbl_id = McMacStatsInitDone_t;
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_stats_init_done));
    DRV_IOR_FIELD(lchip, tbl_id, McMacStatsInitDone_quadSgmac1InitDone_f, &value, &mac_stats_init_done);
    if (0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [McMacStatsInit1.%d] Feature not initialized \n", mac_group_id);
        return CTC_E_NOT_INIT;
    }
#ifndef EMULATOR_ENV
    if (!((SYS_AT_IS_1PP(chip_type)) && ((18 == mac_group_id) || (19 == mac_group_id))))
    {
        tbl_id = McuIntfInitDone_t;
        cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mcu_intf_init_done));
        DRV_IOR_FIELD(lchip, tbl_id, McuIntfInitDone_initDone_f, &value, &mcu_intf_init_done);
        if (0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [McuIntfInit.%d] Feature not initialized \n", mac_group_id);
            return CTC_E_NOT_INIT;
        }
    }
#endif
    return CTC_E_NONE;
}

STATIC int32
_sys_at_datapath_init_module_per_dp(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint32 str_u32 = 0;

    /* set init */
    CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
        NetRxInit_t, NetRxInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
        NetTxInit_t, NetTxInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
        EpeScheduleInit_t, EpeScheduleInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
        BufStoreDataPrepDpInit_t, BufStoreDataPrepDpInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
        BufRetrvPostBrEBInit_t, BufRetrvPostBrEBInit_init_f, 0, 1, &str_u32));

    /* local core */
    CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
        BufRetrvPreBrInit_t, BufRetrvPreBrInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
        BufStoreErmInit_t, BufStoreErmInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
        BufRetrvPostBrPbIntfInit_t, BufRetrvPostBrPbIntfInit_init_f, 0, 1, &str_u32));
    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        /* remote core */
        CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, dp_id, 
            BufRetrvPreBrInit_t, BufRetrvPreBrInit_init_f, 1, 1, &str_u32));
        CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, dp_id, 
            BufStoreErmInit_t, BufStoreErmInit_init_f, 1, 1, &str_u32));
        CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, dp_id, 
            BufRetrvPostBrPbIntfInit_t, BufRetrvPostBrPbIntfInit_init_f, 1, 1, &str_u32));
    }

    CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
        BufStoreMcCtlDpInit_t, BufStoreMcCtlDpInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
        BufStoreUcCtlDpInit_t, BufStoreUcCtlDpInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
        XSecDecInit_t, XSecDecInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
        XSecEncInit_t, XSecEncInit_init_f, 0, 1, &str_u32));

    return CTC_E_NONE;
}

STATIC int32
_sys_at_datapath_init_module_per_dp_check(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint32 value   = 0;
    uint32 str_u32 = 0;

    CTC_ERROR_RETURN(_sys_at_datapath_read_dp_table_field(lchip, core_id, pp_id, dp_id, 
        NetRxInitDone_t, NetRxInitDone_initDone_f, 0, &value, &str_u32));
    if (0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [NetRxInit.%d] Feature not initialized \n", dp_id);
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_dp_table_field(lchip, core_id, pp_id, dp_id, 
        NetTxInitDone_t, NetTxInitDone_initDone_f, 0, &value, &str_u32));
    if (0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [NetTxInit.%d] Feature not initialized \n", dp_id);
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_dp_table_field(lchip, core_id, pp_id, dp_id, 
        EpeScheduleInitDone_t, EpeScheduleInitDone_initDone_f, 0, &value, &str_u32));
    if (0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [EpeScheduleInit.%d] Feature not initialized \n", dp_id);
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_dp_table_field(lchip, core_id, pp_id, dp_id, 
        BufStoreDataPrepDpInitDone_t, BufStoreDataPrepDpInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [BufStoreDataPrepDpInitDone_t %u] Feature not initialized\n", dp_id);
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_dp_table_field(lchip, core_id, pp_id, dp_id, 
        BufRetrvPostBrEBInitDone_t, BufRetrvPostBrEBInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [BufRetrvPostBrEBInitDone_t %u] Feature not initialized\n", dp_id);
        return CTC_E_NOT_INIT;
    }

    /* local core */
    CTC_ERROR_RETURN(_sys_at_datapath_read_dp_table_field(lchip, core_id, pp_id, dp_id, 
        BufRetrvPreBrInitDone_t, BufRetrvPreBrInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [BufRetrvPreBrInitDone_t %u] Feature not initialized\n", dp_id);
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_dp_table_field(lchip, core_id, pp_id, dp_id, 
        BufStoreErmInitDone_t, BufStoreErmInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [BufStoreErmInitDone_t %u] Feature not initialized\n", dp_id);
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_dp_table_field(lchip, core_id, pp_id, dp_id, 
        BufRetrvPostBrPbIntfInitDone_t, BufRetrvPostBrPbIntfInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [BufRetrvPostBrPbIntfInitDone_t %u] Feature not initialized\n", dp_id);
        return CTC_E_NOT_INIT;
    }
    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        /* remote core */
        CTC_ERROR_RETURN(_sys_at_datapath_read_dp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, dp_id, 
            BufRetrvPreBrInitDone_t, BufRetrvPreBrInitDone_initDone_f, 1, &value, &str_u32));
        if(0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [BufRetrvPreBrInitDone_t %u] Feature not initialized\n", dp_id);
            return CTC_E_NOT_INIT;
        }
        CTC_ERROR_RETURN(_sys_at_datapath_read_dp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, dp_id, 
            BufStoreErmInitDone_t, BufStoreErmInitDone_initDone_f, 1, &value, &str_u32));
        if(0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [BufStoreErmInitDone_t %u] Feature not initialized\n", dp_id);
            return CTC_E_NOT_INIT;
        }
        CTC_ERROR_RETURN(_sys_at_datapath_read_dp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, dp_id, 
            BufRetrvPostBrPbIntfInitDone_t, BufRetrvPostBrPbIntfInitDone_initDone_f, 1, &value, &str_u32));
        if(0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [BufRetrvPostBrPbIntfInitDone_t %u] Feature not initialized\n", dp_id);
            return CTC_E_NOT_INIT;
        }
    }

    CTC_ERROR_RETURN(_sys_at_datapath_read_dp_table_field(lchip, core_id, pp_id, dp_id, 
        BufStoreMcCtlDpInitDone_t, BufStoreMcCtlDpInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [BufStoreMcCtlDpInitDone_t %u] Feature not initialized\n", dp_id);
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_dp_table_field(lchip, core_id, pp_id, dp_id, 
        BufStoreUcCtlDpInitDone_t, BufStoreUcCtlDpInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [BufStoreUcCtlDpInitDone_t %u] Feature not initialized\n", dp_id);
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_dp_table_field(lchip, core_id, pp_id, dp_id, 
        XSecDecInitDone_t, XSecDecInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [XSecDecInitDone_t %u] Feature not initialized\n", dp_id);
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_dp_table_field(lchip, core_id, pp_id, dp_id, 
        XSecEncInitDone_t, XSecEncInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [XSecEncInitDone_t %u] Feature not initialized\n", dp_id);
        return CTC_E_NOT_INIT;
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_at_datapath_init_module_per_pp(uint8 lchip, uint8 core_id, uint8 pp_id)
{
    uint8 chip_type = SYS_AT_GET_CHIP_TYPE(lchip);
    uint8 dp_id     = 0;
    uint32 str_u32  = 0;
    MetFifoProcInit_m        met_fifo_proc_init;
    MetFifoShareInit_m       met_fifo_share_init;
    IpeHdrAdjInit_m          ipe_hdr_adj_init;
    IpeIntfMapInit_m         ipe_intf_map_init;
    IpeLkupMgrInit_m         ipe_lkup_mgr_init;
    IpePktProcInit_m         ipe_pkt_proc_init;
    IpeFwdInit_m             ipe_fwd_init;
    DynamicAdInit_m          dnm_ad_init;
    EpeAclOamInit_m          epe_acl_oam_init;
    EpeHdrAdjInit_m          epe_hdr_adj_init;
    EpeHdrProcInit_m         epe_hdr_pro_init;
    EpeNextHopInit_m         epe_next_hop_init;
    QMgrDeqChanInit_m        qmgr_deq_chan_init;
    QMgrDeqL0Init_m          qmgr_deq_l_init;
    QMgrDeqL4CosInit_m       qmgr_deq_l4_cos_init;
    QMgrDeqL4QueInit_m       qmgr_deq_l4_que_init;
    QMgrDeqShpInit_m         qmgr_deq_shp_init;
    QMgrQWriteInit_m         qmgr_qwrite_init;
    EpePktRewriteInit_m      epe_pkt_rewrite_init;

    /* set init */
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        MetFifoProcInit_t, MetFifoProcInit_init_f, 0, 1, &met_fifo_proc_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        MetFifoShareInit_t, MetFifoShareInit_init_f, 0, 1, &met_fifo_share_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        IpeHdrAdjInit_t, IpeHdrAdjInit_init_f, 0, 1, &ipe_hdr_adj_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        IpeIntfMapInit_t, IpeIntfMapInit_init_f, 0, 1, &ipe_intf_map_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        IpeLkupMgrInit_t, IpeLkupMgrInit_init_f, 0, 1, &ipe_lkup_mgr_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        IpePktProcInit_t, IpePktProcInit_init_f, 0, 1, &ipe_pkt_proc_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        IpeFwdInit_t, IpeFwdInit_init_f, 0, 1, &ipe_fwd_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        DynamicAdInit_t, DynamicAdInit_init_f, 0, 1, &dnm_ad_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        EpeAclOamInit_t, EpeAclOamInit_init_f, 0, 1, &epe_acl_oam_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        EpeHdrAdjInit_t, EpeHdrAdjInit_init_f, 0, 1, &epe_hdr_adj_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        EpeHdrProcInit_t, EpeHdrProcInit_init_f, 0, 1, &epe_hdr_pro_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        EpeNextHopInit_t, EpeNextHopInit_init_f, 0, 1, &epe_next_hop_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqL0Init_t, QMgrDeqL0Init_init_f, 0, 1, &qmgr_deq_l_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqL4CosInit_t, QMgrDeqL4CosInit_init_f, 0, 1, &qmgr_deq_l4_cos_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqL4QueInit_t, QMgrDeqL4QueInit_init_f, 0, 1, &qmgr_deq_l4_que_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqShpInit_t, QMgrDeqShpInit_init_f, 0, 1, &qmgr_deq_shp_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        QMgrQWriteInit_t, QMgrQWriteInit_init_f, 0, 1, &qmgr_qwrite_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        EpePktRewriteInit_t, EpePktRewriteInit_init_f, 0, 1, &epe_pkt_rewrite_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        BufStoreMcCtlSliceInit_t, BufStoreMcCtlSliceInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqL4GrpInit_t, QMgrDeqL4GrpInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        CoppIpeInit_t, CoppIpeInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        IpeAclInit_t, IpeAclInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        PolicingIpeInit_t, PolicingIpeInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        CoppEpeInit_t, CoppEpeInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        EpeHdrEditInit_t, EpeHdrEditInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        PolicingEpeInit_t, PolicingEpeInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        DynamicEditInit_t, DynamicEditInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        DynamicKeyInit_t, DynamicKeyInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        EcmpDlbInit_t, EcmpDlbInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        EfdInit_t, EfdInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        EgrSclHashInit_t, EgrSclHashInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        FibEngineInit_t, FibEngineInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        FibHashHost0Init_t, FibHashHost0Init_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        FibHashHost1Init_t, FibHashHost1Init_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        FlexDecodeInit_t, FlexDecodeInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        FlexDecodeInit_t, FlexDecodeInit_init_f, 1, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        FlexDecodeInit_t, FlexDecodeInit_init_f, 2, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        FlowAccAdInit_t, FlowAccAdInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        FlowAccAdInit_t, FlowAccAdInit_init_f, 1, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        FlowAccPpInit_t, FlowAccPpInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        FlowAccPpInit_t, FlowAccPpInit_init_f, 1, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        FlowAccMmuInit_t, FlowAccMmuInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        FlowHashInit_t, FlowHashInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        GlobalStatsInit_t, GlobalStatsInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        IpfixHashInit_t, IpfixHashInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        IpfixHashInit_t, IpfixHashInit_init_f, 1, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        LinkAggInit_t, LinkAggInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        LpmTcamInit_t, LpmTcamInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        MetFifoMsgPreMetInit_t, MetFifoMsgPreMetInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        MplsHashInit_t, MplsHashInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        ParserInit_t, ParserInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        ParserInit_t, ParserInit_init_f, 1, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        ParserInit_t, ParserInit_init_f, 2, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        PpAgingInit_t, PpAgingInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        ProgramEgrAclLtidTcamPartBInit_t, ProgramEgrAclLtidTcamPartBInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        ProgramEgrAclTcamInit_t, ProgramEgrAclTcamInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        ProgramIngAclLtidTcamPartAInit_t, ProgramIngAclLtidTcamPartAInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        ProgramIngAclTcamInit_t, ProgramIngAclTcamInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        StormCtlInit_t, StormCtlInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id,
        SvcPolicingInit_t, SvcPolicingInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        UserIdHashInit_t, UserIdHashInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        UserIdHashTcamInit_t, UserIdHashTcamInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        UserIdTcamInit_t, UserIdTcamInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        DynamicMiscInit_t, DynamicMiscInit_init_f, 0, 1, &str_u32));
    if (!SYS_AT_IS_1PP(chip_type))
    {
        CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
            OamHashInit_t, OamHashInit_init_f, 0, 1, &str_u32));
    }

    /* local core */
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqChanInit_t, QMgrDeqChanInit_init_f, 0, 1, &qmgr_deq_chan_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqGrpMcInit_t, QMgrDeqGrpMcInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqGrpUcInit_t, QMgrDeqGrpUcInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        QMgrLinkListMcInit_t, QMgrLinkListMcInit_init_f, 0, 1, &str_u32));
    CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
        QMgrLinkListUcInit_t, QMgrLinkListUcInit_init_f, 0, 1, &str_u32));

    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        /* remote core */
        CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, 
            QMgrDeqChanInit_t, QMgrDeqChanInit_init_f, 1, 1, &qmgr_deq_chan_init));
        CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, 
            QMgrDeqGrpMcInit_t, QMgrDeqGrpMcInit_init_f, 1, 1, &str_u32));
        CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, 
            QMgrDeqGrpUcInit_t, QMgrDeqGrpUcInit_init_f, 1, 1, &str_u32));
        CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, 
            QMgrLinkListMcInit_t, QMgrLinkListMcInit_init_f, 1, 1, &str_u32));
        CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, 
            QMgrLinkListUcInit_t, QMgrLinkListUcInit_init_f, 1, 1, &str_u32));
    }

    for(dp_id = 0; dp_id < AT_DP_NUM_PER_PP; dp_id++)
    {
        CTC_ERROR_RETURN(_sys_at_datapath_init_module_per_dp(lchip, core_id, pp_id, dp_id));
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_at_datapath_init_module_per_pp_check(uint8 lchip, uint8 core_id, uint8 pp_id)
{
    uint8 chip_type = SYS_AT_GET_CHIP_TYPE(lchip);
    uint8 dp_id     = 0;
    uint32 value    = 0;
    uint32 str_u32  = 0;
    MetFifoProcInitDone_m    met_fifo_proc_init_done;
    MetFifoShareInitDone_m   met_fifo_share_init_done;
    IpeHdrAdjInitDone_m      ipe_hdr_adj_init_done;
    IpeIntfMapInitDone_m     ipe_intf_map_init_done;
    IpeLkupMgrInitDone_m     ipe_lkup_mgr_init_done;
    IpePktProcInitDone_m     ipe_pkt_proc_init_done;
    IpeFwdInitDone_m         ipe_fwd_init_done;
    DynamicAdInitDone_m      dnm_ad_init_done;
    EpeAclOamInitDone_m      epe_acl_oam_init_done;
    EpeHdrAdjInitDone_m      epe_hdr_adj_init_done;
    EpeHdrProcInitDone_m     epe_hdr_pro_init_done;
    EpeNextHopInitDone_m     epe_next_hop_init_done;
    QMgrDeqChanInitDone_m    qmgr_deq_chan_init_done;
    QMgrDeqL0InitDone_m      qmgr_deq_l_init_done;
    QMgrDeqL4CosInitDone_m   qmgr_deq_l4_cos_init_done;
    QMgrDeqL4QueInitDone_m   qmgr_deq_l4_que_init_done;
    QMgrDeqShpInitDone_m     qmgr_deq_shp_init_done;
    QMgrQWriteInitDone_m     qmgr_qwrite_init_done;
    EpePktRewriteInitDone_m  epe_pkt_rewrite_init_done;

    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        MetFifoProcInitDone_t, MetFifoProcInitDone_initDone_f, 0, &value, &met_fifo_proc_init_done));
    if (0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [MetFifoProcInit.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        MetFifoShareInitDone_t, MetFifoShareInitDone_initDone_f, 0, &value, &met_fifo_share_init_done));
    if (0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [MetFifoShareInit.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        IpeHdrAdjInitDone_t, IpeHdrAdjInitDone_initDone_f, 0, &value, &ipe_hdr_adj_init_done));
    if (0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [IpeHdrAdjInit.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        IpeIntfMapInitDone_t, IpeIntfMapInitDone_initDone_f, 0, &value, &ipe_intf_map_init_done));
    if (0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [IpeIntfMapInit.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        IpeLkupMgrInitDone_t, IpeLkupMgrInitDone_initDone_f, 0, &value, &ipe_lkup_mgr_init_done));
    if (0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [IpeLkupMgrInit.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        IpePktProcInitDone_t, IpePktProcInitDone_initDone_f, 0, &value, &ipe_pkt_proc_init_done));
    if (0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [IpePktProcInit.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        IpeFwdInitDone_t, IpeFwdInitDone_initDone_f, 0, &value, &ipe_fwd_init_done));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [IpeFwdInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        DynamicAdInitDone_t, DynamicAdInitDone_initDone_f, 0, &value, &dnm_ad_init_done));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [DynamicAdInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        EpeAclOamInitDone_t, EpeAclOamInitDone_initDone_f, 0, &value, &epe_acl_oam_init_done));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [EpeAclOamInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        EpeHdrAdjInitDone_t, EpeHdrAdjInitDone_initDone_f, 0, &value, &epe_hdr_adj_init_done));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [EpeHdrAdjInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        EpeHdrProcInitDone_t, EpeHdrProcInitDone_initDone_f, 0, &value, &epe_hdr_pro_init_done));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [EpeHdrProcInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        EpeNextHopInitDone_t, EpeNextHopInitDone_initDone_f, 0, &value, &epe_next_hop_init_done));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [EpeNextHopInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqL0InitDone_t, QMgrDeqL0InitDone_initDone_f, 0, &value, &qmgr_deq_l_init_done));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrDeqL0InitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqL4CosInitDone_t, QMgrDeqL4CosInitDone_initDone_f, 0, &value, &qmgr_deq_l4_cos_init_done));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrDeqL4CosInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqL4QueInitDone_t, QMgrDeqL4QueInitDone_initDone_f, 0, &value, &qmgr_deq_l4_que_init_done));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrDeqL4QueInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqShpInitDone_t, QMgrDeqShpInitDone_initDone_f, 0, &value, &qmgr_deq_shp_init_done));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrDeqShpInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        QMgrQWriteInitDone_t, QMgrQWriteInitDone_initDone_f, 0, &value, &qmgr_qwrite_init_done));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrQWriteInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        EpePktRewriteInitDone_t, EpePktRewriteInitDone_initDone_f, 0, &value, &epe_pkt_rewrite_init_done));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [EpePktRewriteInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        BufStoreMcCtlSliceInitDone_t, BufStoreMcCtlSliceInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [BufStoreMcCtlSliceInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqL4GrpInitDone_t, QMgrDeqL4GrpInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrDeqL4GrpInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        CoppIpeInitDone_t, CoppIpeInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [CoppIpeInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        IpeAclInitDone_t, IpeAclInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [IpeAclInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        PolicingIpeInitDone_t, PolicingIpeInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [PolicingIpeInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        CoppEpeInitDone_t, CoppEpeInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [CoppEpeInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        EpeHdrEditInitDone_t, EpeHdrEditInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [EpeHdrEditInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        PolicingEpeInitDone_t, PolicingEpeInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [PolicingEpeInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        DynamicEditInitDone_t, DynamicEditInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [DynamicEditInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        DynamicKeyInitDone_t, DynamicKeyInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [DynamicKeyInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        EcmpDlbInitDone_t, EcmpDlbInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [EcmpDlbInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        EfdInitDone_t, EfdInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [EfdInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        EgrSclHashInitDone_t, EgrSclHashInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [EgrSclHashInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        FibEngineInitDone_t, FibEngineInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FibEngineInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        FibHashHost0InitDone_t, FibHashHost0InitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FibHashHost0Init] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        FibHashHost1InitDone_t, FibHashHost1InitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FibHashHost1Init] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        FlexDecodeInitDone_t, FlexDecodeInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FlexDecodeInit.0] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        FlexDecodeInitDone_t, FlexDecodeInitDone_initDone_f, 1, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FlexDecodeInit.1] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        FlexDecodeInitDone_t, FlexDecodeInitDone_initDone_f, 2, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FlexDecodeInit.2] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        FlowAccAdInitDone_t, FlowAccAdInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FlowAccAdInit.0] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        FlowAccAdInitDone_t, FlowAccAdInitDone_initDone_f, 1, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FlowAccAdInit.1] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        FlowAccPpInitDone_t, FlowAccPpInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FlowAccPpInit.0] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        FlowAccPpInitDone_t, FlowAccPpInitDone_initDone_f, 1, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FlowAccPpInit.1] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        FlowAccMmuInitDone_t, FlowAccMmuInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FlowAccMmuInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        FlowHashInitDone_t, FlowHashInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FlowHashInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        GlobalStatsInitDone_t, GlobalStatsInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [GlobalStatsInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        IpfixHashInitDone_t, IpfixHashInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [IpfixHashInit.0] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        IpfixHashInitDone_t, IpfixHashInitDone_initDone_f, 1, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [IpfixHashInit.1] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        LinkAggInitDone_t, LinkAggInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [LinkAggInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        LpmTcamInitDone_t, LpmTcamInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [LpmTcamInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        MetFifoMsgPreMetInitDone_t, MetFifoMsgPreMetInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [MetFifoMsgPreMetInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        MplsHashInitDone_t, MplsHashInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [MplsHashInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        ParserInitDone_t, ParserInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [ParserInit.0] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        ParserInitDone_t, ParserInitDone_initDone_f, 1, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [ParserInit.1] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        ParserInitDone_t, ParserInitDone_initDone_f, 2, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [ParserInit.2] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        PpAgingInitDone_t, PpAgingInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [PpAgingInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        ProgramEgrAclLtidTcamPartBInitDone_t, ProgramEgrAclLtidTcamPartBInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [ProgramEgrAclLtidTcamPartBInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        ProgramEgrAclTcamInitDone_t, ProgramEgrAclTcamInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [ProgramEgrAclTcamInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        ProgramIngAclLtidTcamPartAInitDone_t, ProgramIngAclLtidTcamPartAInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [ProgramIngAclLtidTcamPartAInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        ProgramIngAclTcamInitDone_t, ProgramIngAclTcamInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [ProgramIngAclTcamInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        StormCtlInitDone_t, StormCtlInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [StormCtlInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        SvcPolicingInitDone_t, SvcPolicingInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [SvcPolicingInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        UserIdHashInitDone_t, UserIdHashInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [UserIdHashInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        UserIdHashTcamInitDone_t, UserIdHashTcamInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [UserIdHashTcamInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        UserIdTcamInitDone_t, UserIdTcamInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [UserIdTcamInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        DynamicMiscInitDone_t, DynamicMiscInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [DynamicMiscInitDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    if (!SYS_AT_IS_1PP(chip_type))
    {
        CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
            OamHashInitDone_t, OamHashInitDone_initDone_f, 0, &value, &str_u32));
        if(0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [OamHashInit] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
    }

    /* local core */
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqChanInitDone_t, QMgrDeqChanInitDone_initDone_f, 0, &value, &qmgr_deq_chan_init_done));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrDeqChanInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqGrpMcInitDone_t, QMgrDeqGrpMcInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrDeqGrpMcInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        QMgrDeqGrpUcInitDone_t, QMgrDeqGrpUcInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrDeqGrpUcInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        QMgrLinkListMcInitDone_t, QMgrLinkListMcInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrLinkListMcInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, core_id, pp_id, 
        QMgrLinkListUcInitDone_t, QMgrLinkListUcInitDone_initDone_f, 0, &value, &str_u32));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrLinkListUcInit] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        /* remote core */
        CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, 
            QMgrDeqChanInitDone_t, QMgrDeqChanInitDone_initDone_f, 1, &value, &qmgr_deq_chan_init_done));
        if(0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrDeqChanInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, 
            QMgrDeqGrpMcInitDone_t, QMgrDeqGrpMcInitDone_initDone_f, 1, &value, &str_u32));
        if(0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrDeqGrpMcInit] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, 
            QMgrDeqGrpUcInitDone_t, QMgrDeqGrpUcInitDone_initDone_f, 1, &value, &str_u32));
        if(0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrDeqGrpUcInit] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, 
            QMgrLinkListMcInitDone_t, QMgrLinkListMcInitDone_initDone_f, 1, &value, &str_u32));
        if(0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrLinkListMcInit] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        CTC_ERROR_RETURN(_sys_at_datapath_read_pp_table_field(lchip, ((0 == core_id) ? 1 : 0), pp_id, 
            QMgrLinkListUcInitDone_t, QMgrLinkListUcInitDone_initDone_f, 1, &value, &str_u32));
        if(0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrLinkListUcInit] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
    }

    for(dp_id = 0; dp_id < AT_DP_NUM_PER_PP; dp_id++)
    {
        CTC_ERROR_RETURN(_sys_at_datapath_init_module_per_dp_check(lchip, core_id, pp_id, dp_id));
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_at_datapath_init_module_per_core(uint8 lchip, uint8 core_id)
{
    uint8 chip_type     = SYS_AT_GET_CHIP_TYPE(lchip);
    uint8  pp_id        = 0;
    uint8  mac_group_id = 0;
    QMgrQueEntryMcDrainEnable_m qmgr_drain_en;
    BufStoreProcMcInit_m        bsmc_init;
    BufStoreProcUcInit_m        bsuc_init;
    BufRetrvGlbWrrInit_m        br_wrr_init;
    QMgrQueEntryMcInit_m        q_mc_init;
    QMgrQueEntryUcInit_m        q_uc_init;
    QMgrErmInit_m               q_erm_init;
    FibAccInit_m                fib_init;
    MetFifoMsgInit_m            met_init;
    MetFifoMsgConflictWrInit_m  met_wr_init;
    MetFifoRcdInit_m            rcd_init;
    OamFwdInit_m                oam_f_init;
    OamProcInit_m               oam_p_init;
    OamAutoGenInit_m            oam_a_init;
    MdioInit_m                  mdio_init;
    DmaCtlInit_m                dma_ctl_init;
    CpuMapInit_m                cpu_map_init;

    /* set init */
    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
        BufStoreProcMcInit_t, BufStoreProcMcInit_init_f, 0, 1, &bsmc_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
        BufStoreProcUcInit_t, BufStoreProcUcInit_init_f, 0, 1, &bsuc_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
        BufRetrvGlbWrrInit_t, BufRetrvGlbWrrInit_init_f, 0, 1, &br_wrr_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
        QMgrQueEntryMcInit_t, QMgrQueEntryMcInit_init_f, 0, 1, &q_mc_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
        QMgrQueEntryUcInit_t, QMgrQueEntryUcInit_init_f, 0, 1, &q_uc_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
        QMgrErmInit_t, QMgrErmInit_init_f, 0, 1, &q_erm_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
        FibAccInit_t, FibAccInit_init_f, 0, 1, &fib_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
        MetFifoMsgInit_t, MetFifoMsgInit_init_f, 0, 1, &met_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
        MetFifoMsgConflictWrInit_t, MetFifoMsgConflictWrInit_init_f, 0, 1, &met_wr_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
        MetFifoRcdInit_t, MetFifoRcdInit_init_f, 0, 1, &rcd_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
        MdioInit_t, MdioInit_init_f, 0, 1, &mdio_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
        DmaCtlInit_t, DmaCtlInit_init_f, 0, 1, &dma_ctl_init));
    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
        CpuMapInit_t, CpuMapInit_init_f, 0, 1, &cpu_map_init));
    if (!SYS_AT_IS_1PP(chip_type))
    {
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            OamFwdInit_t, OamFwdInit_init_f, 0, 1, &oam_f_init));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            OamProcInit_t, OamProcInit_init_f, 0, 1, &oam_p_init));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            OamAutoGenInit_t, OamAutoGenInit_init_f, 0, 1, &oam_a_init));
    }

    for(pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
    {
        SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));
        CTC_ERROR_RETURN(_sys_at_datapath_init_module_per_pp(lchip, core_id, pp_id));
    }

    for(mac_group_id = 0; mac_group_id < AT_MCMAC_NUM_PER_CORE; mac_group_id++)
    {
        SYS_CONDITION_CONTINUE(!SYS_AT_MAC_GROUP_IS_VAILD(lchip, core_id, mac_group_id));
        CTC_ERROR_RETURN(_sys_at_datapath_init_module_per_mac_group(lchip, core_id, mac_group_id));
    }

#ifdef AT_CPUMAC
        CTC_ERROR_RETURN(_sys_at_datapath_init_module_cpumac(lchip, core_id));
#endif

    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
        QMgrQueEntryMcDrainEnable_t, QMgrQueEntryMcDrainEnable_freePtrDrainEnable_f, 0, 0xffffffff, &qmgr_drain_en));

    return CTC_E_NONE;
}

STATIC int32
_sys_at_datapath_init_module_per_core_check(uint8 lchip, uint8 core_id)
{
    uint8 chip_type     = SYS_AT_GET_CHIP_TYPE(lchip);
    uint8  pp_id        = 0;
    uint8  mac_group_id = 0;
    uint32 value        = 0;
    BufStoreProcMcInitDone_m       bsmc_init_d;
    BufStoreProcUcInitDone_m       bsuc_init_d;
    BufRetrvGlbWrrInitDone_m       br_wrr_init_d;
    QMgrQueEntryMcInitDone_m       q_mc_init_d;
    QMgrQueEntryUcInitDone_m       q_uc_init_d;
    QMgrErmInitDone_m              q_erm_init_d;
    FibAccInitDone_m               fib_init_d;
    MetFifoMsgInitDone_m           met_init_d;
    MetFifoMsgConflictWrInitDone_m met_wr_init_d;
    MetFifoRcdInitDone_m           rcd_init_d;
    OamFwdInitDone_m               oam_f_init_d;
    OamProcInitDone_m              oam_p_init_d;
    OamAutoGenInitDone_m           oam_a_init_d;
    MdioInitDone_m                 mdio_init_done;
    DmaCtlInitDone_m               dma_ctl_init_done;
    CpuMapInitDone_m               cpu_map_init_done;
    

    CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
        BufStoreProcMcInitDone_t, BufStoreProcMcInitDone_initDone_f, 0, &value, &bsmc_init_d));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [BufStoreProcMcInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
        BufStoreProcUcInitDone_t, BufStoreProcUcInitDone_initDone_f, 0, &value, &bsuc_init_d));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [BufStoreProcUcInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
        BufRetrvGlbWrrInitDone_t, BufRetrvGlbWrrInitDone_initDone_f, 0, &value, &br_wrr_init_d));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [BufRetrvGlbWrrInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
        QMgrQueEntryMcInitDone_t, QMgrQueEntryMcInitDone_initDone_f, 0, &value, &q_mc_init_d));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrQueEntryMcInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
        QMgrQueEntryUcInitDone_t, QMgrQueEntryUcInitDone_initDone_f, 0, &value, &q_uc_init_d));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrQueEntryUcInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
        QMgrErmInitDone_t, QMgrErmInitDone_initDone_f, 0, &value, &q_erm_init_d));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [QMgrErmInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
        FibAccInitDone_t, FibAccInitDone_initDone_f, 0, &value, &fib_init_d));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [FibAccInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
        MetFifoMsgInitDone_t, MetFifoMsgInitDone_initDone_f, 0, &value, &met_init_d));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [MetFifoMsgInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
        MetFifoMsgConflictWrInitDone_t, MetFifoMsgConflictWrInitDone_initDone_f, 0, &value, &met_wr_init_d));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [MetFifoMsgConflictWrInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
        MetFifoRcdInitDone_t, MetFifoRcdInitDone_initDone_f, 0, &value, &rcd_init_d));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [MetFifoRcdInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
        MdioInitDone_t, MdioInitDone_initDone_f, 0, &value, &mdio_init_done));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [MdioInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }
    /*special operation for wb reload: skip DmaCtlInitDone check in wb reload*/
    if(p_drv_master[lchip]->wb_status != DRV_WB_STATUS_RELOADING)
    {
        CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
            DmaCtlInitDone_t, DmaCtlInitDone_initDone_f, 0, &value, &dma_ctl_init_done));
        if(0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [DmaCtlInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
        CpuMapInitDone_t, CpuMapInitDone_initDone_f, 0, &value, &cpu_map_init_done));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [CpuMapInitDone.initDone] Feature not initialized \n");
        return CTC_E_NOT_INIT;
    }

    if (!SYS_AT_IS_1PP(chip_type))
    {
        CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
            OamFwdInitDone_t, OamFwdInitDone_initDone_f, 0, &value, &oam_f_init_d));
        if(0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [OamFwdInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
            OamProcInitDone_t, OamProcInitDone_initDone_f, 0, &value, &oam_p_init_d));
        if(0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [OamProcInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
        CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
            OamAutoGenInitDone_t, OamAutoGenInitDone_initDone_f, 0, &value, &oam_a_init_d));
        if(0 == value)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [OamAutoGenInitDone.initDone] Feature not initialized \n");
            return CTC_E_NOT_INIT;
        }
    }

    for(pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
    {
        SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));
        CTC_ERROR_RETURN(_sys_at_datapath_init_module_per_pp_check(lchip, core_id, pp_id));
    }

    for(mac_group_id = 0; mac_group_id < AT_MCMAC_NUM_PER_CORE; mac_group_id++)
    {
        SYS_CONDITION_CONTINUE(!SYS_AT_MAC_GROUP_IS_VAILD(lchip, core_id, mac_group_id));
        CTC_ERROR_RETURN(_sys_at_datapath_init_module_per_mac_group_check(lchip, core_id, mac_group_id));
    }

#ifdef AT_CPUMAC
        CTC_ERROR_RETURN(_sys_at_datapath_init_module_cpumac_check(lchip, core_id));
#endif

    return CTC_E_NONE;
}

#endif

STATIC int32
_sys_at_datapath_init_module(uint8 lchip)
{
    uint8 core_id      = 0;
    uint8 core_num     = 1;
#ifdef PCS_ONLY
    uint8 mac_group_id  = 0;
    uint8 pp_id         = 0;
    uint8 dp_id         = 0;
    uint32 value        = 0;

    uint32 cmd          = 0;
    QuadSgmacInit_m     quad_sgmac_init;

#endif
    DP_DEBUG_FUNCTION_CALLED_PRINT();

    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "### %s enter\n", __FUNCTION__);

    core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

    for (core_id = 0; core_id < core_num; core_id++)
    {
#ifdef PCS_ONLY
        for (mac_group_id = 0; mac_group_id < AT_MCMAC_NUM_PER_CORE; mac_group_id++)
        {
            if (!SYS_AT_MAC_GROUP_IS_VAILD(lchip, core_id, mac_group_id))
            {
                continue;
            }

            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_stats_init_reg(lchip, core_id, mac_group_id));
            CTC_ERROR_RETURN(_sys_at_mac_set_mcmac_init_reg(lchip, core_id, mac_group_id));
        }

        value = 1;
        cmd    = DRV_IOR(QuadSgmacInit_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &quad_sgmac_init));
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, QuadSgmacInit_t, 0, QuadSgmacInit_init_f, &value, &quad_sgmac_init);
        cmd    = DRV_IOW(QuadSgmacInit_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &quad_sgmac_init));

        for (pp_id = 0; pp_id < 2; pp_id++)
        {
            for (dp_id = 0; dp_id < 2; dp_id++)
            {
                CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
                    NetRxInit_t, NetRxInit_init_f, 0, 1, &value));
                CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
                    NetTxInit_t, NetTxInit_init_f, 0, 1, &value));
            }
        }

        sal_task_sleep(2000);
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "delay 2000\n");
#else
#if (SDB_MEM_MODEL != SDB_MODE)

        CTC_ERROR_RETURN(_sys_at_datapath_init_module_per_core(lchip, core_id));
        SYS_CONDITION_RETURN((1 == SDK_WORK_PLATFORM), CTC_E_NONE);
#ifdef EMULATION_ENV
        sal_task_sleep(1000);
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "delay 1000\n");
#else
        sal_task_sleep(1);
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "delay 1\n");
#endif
        CTC_ERROR_RETURN(_sys_at_datapath_init_module_per_core_check(lchip, core_id));

#endif
#endif
    }

    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "### %s end\n", __FUNCTION__);

    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

int32
_sys_at_datapath_init_manual_patch(uint8 lchip)
{
    uint8  core_id     = 0;
    uint8  core_num    = 1;
    uint8  pp_id       = 0;
    uint8  dp_id       = 0;
    uint8 chip_type    = SYS_AT_GET_CHIP_TYPE(lchip);
    uint32 value       = 0;
    IpeAclMiscCtl_m       ipe_acl_misc_ctl;
    IpeHdrAdjCreditCtl_m  ipe_hdr_credit_ctl;
    LinkAggMiscCtl_m      link_agg_misc_ctl;
    CpuMapFifoCtl_m       cpu_map_fifo_ctl;
    QMgrDeqCreditScanCtl_m qmgr_deq_credit_ctl;
    QMgrDeqReqStallCtl_m   qmgr_deq_req_ctl;
    NetRxMiscCtl_m        netrx_misc_ctl;
    McQWriteSpanOnDropCtl_m mc_q_ctl;
    PbCtlBrRdLatency_m    pb_ctl_latency;
    CtcDpRxCtlClockEn_m   ctc_dp_rx_clk_en;
    NetRxCtl_m            netrx_ctl;
    EpeScheduleMiscCtl_m  epe_sch_misc_ctl;
    CtcDpTxCtlClockEn_m   ctc_dp_tx_clk_en;
    NetRxAdmissionCfg_m   netrx_adm_cfg;
    CoreAgingCreditCtl_m  core_ag_credit_ctl;

    core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

    for (core_id = 0; core_id < core_num; core_id++)
    {
        if (!SYS_AT_IS_1PP(chip_type))
        {
            CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                CoreAgingCreditCtl_t, CoreAgingCreditCtl_coreAgingSynThrd_f, 0, 16, &core_ag_credit_ctl));
            CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                CoreAgingCreditCtl_t, CoreAgingCreditCtl_coreAgingDeskewSynThrd_f, 0, 16, &core_ag_credit_ctl));
        }

        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            CpuMapFifoCtl_t, CpuMapFifoCtl_encapMapPktFifoAFullThrd_f, 0, 8, &cpu_map_fifo_ctl));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            QMgrDeqReqStallCtl_t, QMgrDeqReqStallCtl_cfgScanEn_f, 0, 0, &qmgr_deq_req_ctl));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            McQWriteSpanOnDropCtl_t, McQWriteSpanOnDropCtl_sodDest_channelId_f, 0, 63, &mc_q_ctl));
#if defined(EMULATION_ENV) && (EMULATOR_ENV == 0)
        /* 1pp/2pp */
        value = 5;
#else
        /* Emulator/Uml/Demo */
        value = 6;
#endif
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            PbCtlBrRdLatency_t, PbCtlBrRdLatency_brRdDataLatency_f, 0, value, &pb_ctl_latency));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            PbCtlBrRdLatency_t, PbCtlBrRdLatency_brRdDataLatency_f, 1, value, &pb_ctl_latency));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            PbCtlBrRdLatency_t, PbCtlBrRdLatency_brRdDataLatency_f, 2, value, &pb_ctl_latency));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            PbCtlBrRdLatency_t, PbCtlBrRdLatency_brRdDataLatency_f, 3, value, &pb_ctl_latency));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            PbCtlBrRdLatency_t, PbCtlBrRdLatency_brRdEnLatency_f, 0, value, &pb_ctl_latency));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            PbCtlBrRdLatency_t, PbCtlBrRdLatency_brRdEnLatency_f, 1, value, &pb_ctl_latency));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            PbCtlBrRdLatency_t, PbCtlBrRdLatency_brRdEnLatency_f, 2, value, &pb_ctl_latency));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            PbCtlBrRdLatency_t, PbCtlBrRdLatency_brRdEnLatency_f, 3, value, &pb_ctl_latency));

        for(pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));

            CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
                IpeAclMiscCtl_t, IpeAclMiscCtl_seqCheckEn_f, 0, 1, &ipe_acl_misc_ctl));
            CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
                IpeHdrAdjCreditCtl_t, IpeHdrAdjCreditCtl_userIdProcessFifoCreditThrd_f, 0, 37, &ipe_hdr_credit_ctl));
            CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
                LinkAggMiscCtl_t, LinkAggMiscCtl_asyncCrossCoreInputFifoNorThrd_f, 0, 16, &link_agg_misc_ctl));
            CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
                LinkAggMiscCtl_t, LinkAggMiscCtl_asyncCrossCoreOutputFifoNorThrd_f, 0, 16, &link_agg_misc_ctl));
            CTC_ERROR_RETURN(_sys_at_datapath_write_pp_table_field(lchip, core_id, pp_id, 
                QMgrDeqCreditScanCtl_t, QMgrDeqCreditScanCtl_cfgQMgrDeqScanEn_f, 0, 0, &qmgr_deq_credit_ctl));

            for(dp_id = 0; dp_id < AT_DP_NUM_PER_PP; dp_id++)
            {
                CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
                    NetRxMiscCtl_t, NetRxMiscCtl_cfgMiscAllowLength_f, 0, 64, &netrx_misc_ctl));
                CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
                    NetRxAdmissionCfg_t, NetRxAdmissionCfg_cfgLongPktPri_f, 0, 1, &netrx_adm_cfg));
                CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
                    EpeScheduleMiscCtl_t, EpeScheduleMiscCtl_cfgXSecGlobalEn_f, 0, 0, &epe_sch_misc_ctl));

#ifdef EMULATION_ENV
#ifndef EMULATOR_ENV
                /* 2pp pp2 dp0 config 1 */
                if ((2 == pp_id) && (0 == dp_id))
                {
                    CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
                        EpeScheduleMiscCtl_t, EpeScheduleMiscCtl_cfgXSecGlobalEn_f, 0, 1, &epe_sch_misc_ctl));
                }
#endif
                /* 1pp/2pp/Emulator */
                CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
                    CtcDpRxCtlClockEn_t, CtcDpRxCtlClockEn_enClkXSecDec_f, 0, 1, &ctc_dp_rx_clk_en));
                CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
                    NetRxCtl_t, NetRxCtl_cfgXSecDecEnable_f, 0, 1, &netrx_ctl));
                CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
                    CtcDpTxCtlClockEn_t, CtcDpTxCtlClockEn_enClkXSecEnc_f, 0, 1, &ctc_dp_tx_clk_en));
#else
                /* Uml/Demo */
                CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
                    CtcDpRxCtlClockEn_t, CtcDpRxCtlClockEn_enClkXSecDec_f, 0, 0, &ctc_dp_rx_clk_en));
                CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
                    NetRxCtl_t, NetRxCtl_cfgXSecDecEnable_f, 0, 0, &netrx_ctl));
                CTC_ERROR_RETURN(_sys_at_datapath_write_dp_table_field(lchip, core_id, pp_id, dp_id, 
                    CtcDpTxCtlClockEn_t, CtcDpTxCtlClockEn_enClkXSecEnc_f, 0, 0, &ctc_dp_tx_clk_en));
#endif
            }
        }
    }

    return CTC_E_NONE;
}

uint8
sys_at_datapath_mac_group_is_valid(uint8 lchip, uint8 core_id, uint8 mac_group_id)
{
    uint32 mac_group_valid = 0;
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_mac_group_valid(lchip, core_id, &mac_group_valid));
    return ((mac_group_valid & (0x1 << mac_group_id)) ? TRUE : FALSE);
}

uint8
sys_at_datapath_pp_is_valid(uint8 lchip, uint8 core_id, uint8 pp_id)
{
    uint8 pp_valid[DMPS_MAX_CORE_NUM] = {0, 0};
    uint8 chip_type = SYS_AT_GET_CHIP_TYPE(lchip);

    switch (chip_type)
    {
        case DRV_CHIP_SUB_TYPE_2:
#ifdef EMULATION_ENV
            pp_valid[0] = 0x6;
            pp_valid[1] = 0x0;
#else
            pp_valid[0] = 0x7;
            pp_valid[1] = 0x0;
#endif
            break;
        case DRV_CHIP_SUB_TYPE_1:
#ifdef EMULATION_ENV
#ifdef PCS_ONLY
            pp_valid[0] = 0x3;
            pp_valid[1] = 0x0;
#else
            pp_valid[0] = 0xc;
            pp_valid[1] = 0x0;
#endif
#else
            if (AT_CHIP_IS_SERDES_PG_LOW(lchip))
            {
                pp_valid[0] = 0x7;
                pp_valid[1] = 0x0;
            }
            else
            {
                pp_valid[0] = 0xf;
                pp_valid[1] = 0x0;
            }
#endif
            break;
        case DRV_CHIP_SUB_TYPE_3:
            if (AT_CHIP_IS_SERDES_DCM_PG_LOW(lchip))
            {
                pp_valid[0] = 0x7;
                pp_valid[1] = 0x7;
            }
            else
            {
                pp_valid[0] = 0xf;
                pp_valid[1] = 0xf;
            }
            break;
        case DRV_CHIP_SUB_TYPE_4:
#ifdef EMULATOR_ENV
            pp_valid[0] = 0x8;
            pp_valid[1] = 0x8;
#else
            pp_valid[0] = 0x7;
            pp_valid[1] = 0x7;
#endif
            break;
        case SYS_AT_SUBTYPE_1PP:
            pp_valid[0] = 0x8;
            pp_valid[1] = 0x0;
            break;
        default:
            break;
    }

    return ((pp_valid[core_id] & (0x1 << pp_id)) ? TRUE : FALSE);
}

int32
_sys_at_datapath_mapping_cfg_to_none(uint8 lchip, uint16 src_dport)
{
    uint8  cnt                = 0;
    uint8  serdes_num         = 0;
    uint8  if_mode            = 0;
    uint8  port_type          = 0;
    uint16 psd                = 0;
    uint16 lsd                = 0;
    uint16 src_mac            = 0;
    uint16 src_pcs            = 0;
    uint16 src_lsd            = 0;
    uint16 src_chan           = 0;
    uint16 src_chan_rx        = 0;
    sys_dmps_db_upt_info_t port_info  = {0};
    sys_dmps_db_upt_info_t upt_info_p = {0};

    if (!sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, src_dport))
    {
        return CTC_E_INVALID_PARAM;
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, src_dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_MODE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_MAC_ID,        src_mac);
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_PCS_ID,        src_pcs);
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_CHAN_ID,       src_chan);
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_CHAN_RX_ID,    src_chan_rx);
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES,  src_lsd);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE, if_mode);

    SYS_AT_GET_SERDES_NUM_BY_MODE(if_mode, serdes_num);
    port_type = SYS_DMPS_RSV_PORT;

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &upt_info_p));
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_DPORT,         src_dport);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_CHAN_ID,       src_chan);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_CHAN_RX_ID,    src_chan_rx);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_IF_MODE,       CTC_CHIP_SERDES_NONE_MODE);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_TYPE,          port_type);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_IF_TYPE,       CTC_PORT_IF_NONE);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_FEC_TYPE,      SYS_DMPS_FEC_TYPE_NONE);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_LINK_FSM,      PMA_RX_NONREADY);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_LINK_MODE,     g_port_link_mode);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_CHAN_SPEED_MODE,    SYS_PORT_SPEED_MAX);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_CHAN_RX_SPEED_MODE, SYS_PORT_SPEED_MAX);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_CHAN_SPEED_VALUE,   0);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_CHAN_RX_SPEED_VALUE,0);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_IS_AN_FIRST,   0);
    CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &upt_info_p));

    for (cnt = 0; cnt < serdes_num; cnt++)
    {
        lsd = src_lsd + cnt;
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_LSD, lsd,
            DMPS_DB_TYPE_PSD, NULL, &psd));

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &upt_info_p));
        DMPS_DB_SET_MAP_UPDATE(upt_info_p);
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_DPORT,         src_dport);
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_MAC_ID,        src_mac);
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_PCS_ID,        src_pcs);
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_CHAN_ID,       src_chan);
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_CHAN_RX_ID,    src_chan_rx);
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_LOGIC_SERDES,  lsd);
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_PHYSIC_SERDES, psd);

        DMPS_DB_SET_PROPERTY_UPDATE(upt_info_p, DMPS_DB_LSD_PCSL_IDX);
        DMPS_DB_SET_PROPERTY_UPDATE(upt_info_p, DMPS_DB_PSD_SPEED);

#ifdef PCS_ONLY
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_DPORT,      src_dport + cnt);
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_CHAN_ID,    src_chan + cnt);
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_CHAN_RX_ID, src_chan_rx + cnt);
#endif
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_MAC_ID,            src_mac + cnt);
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_PCS_ID,            src_pcs + cnt);
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_LOGIC_SERDES,      lsd);
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_PHYSIC_SERDES,     psd);

        CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &upt_info_p));
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_delete_relation(uint8 lchip, uint16 logical_serdes)
{
    uint16 dport   = 0;
    uint16 chan_id = 0;
    uint16 mac_id  = 0;
    uint16 pcs_id  = 0;
    uint16 psd     = 0;
    sys_dmps_db_upt_info_t port_info  = {0};
    sys_dmps_db_upt_info_t upt_info_p = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES, logical_serdes);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_DPORT,         dport);
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_MAC_ID,        mac_id);
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_PCS_ID,        pcs_id);
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_CHAN_ID,       chan_id);
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_PHYSIC_SERDES, psd);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &upt_info_p));
    DMPS_DB_SET_MAP_UPDATE(upt_info_p);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_DPORT,         dport);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_MAC_ID,        mac_id);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_PCS_ID,        pcs_id);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_CHAN_ID,       chan_id);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_CHAN_RX_ID,    chan_id);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_LOGIC_SERDES,  logical_serdes);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_PHYSIC_SERDES, psd);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_MAC_ID,            mac_id);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_PCS_ID,            pcs_id);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_LOGIC_SERDES,      logical_serdes);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_PHYSIC_SERDES,     psd);

    CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &upt_info_p));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_dynamic_switch_to_none(uint8 lchip, sys_dmps_ds_list_t* target, uint8 is_switch_serdes)
{
    uint8  dport_num    = 0;
    uint8  lsd_num      = 0;
    uint16 logic_serdes = 0;
    uint16 mac_id       = 0;

    DP_DEBUG_FUNCTION_CALLED_PRINT();
#ifdef PCS_ONLY
    uint16 chan_id   = 0;
#endif

    if (0 == target->src_dport_num)
    {
        return CTC_E_NONE;
    }

    if (is_switch_serdes)
    {
        for(dport_num = 0; dport_num < target->src_dport_num; dport_num++)
        {
            CTC_ERROR_RETURN(sys_at_mcu_del_port_mapping(lchip, target->src_dport_list[dport_num]));
        }
    }
    
    /* 1. change database */
    for(dport_num = 0; dport_num < target->src_dport_num; dport_num++)
    {
        CTC_ERROR_RETURN(_sys_at_datapath_mapping_cfg_to_none(lchip, target->src_dport_list[dport_num]));
    }

    /* 2. config MAC/PCS/HATA register to NONE mode */
    for (lsd_num = 0; lsd_num < target->lsd_num; lsd_num++)
    {
        logic_serdes = target->lsd_list[lsd_num];
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_LSD, logic_serdes, DMPS_DB_TYPE_MAC, NULL, &mac_id));
        if (SYS_AT_IS_NW_SERDES(logic_serdes))
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_nw_config_by_mac_id(lchip, mac_id));
        }
        else
        {
#ifdef AT_CPUMAC
            CTC_ERROR_RETURN(_sys_at_cpumac_set_mac_config(lchip, mac_id));
#endif
        }
    }

#if ((!defined(EMULATION_ENV) && (0 == SDK_WORK_PLATFORM)) || defined(AT_SERDES_SIM))
    if (is_switch_serdes)
    {
        uint16 serdes_id    = 0;
        /* TBD: 3. config serdes */
        for (lsd_num = 0; lsd_num < target->lsd_num; lsd_num++)
        {
            logic_serdes = target->lsd_list[lsd_num];   
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_LSD, logic_serdes, DMPS_DB_TYPE_PSD, NULL, &serdes_id));
            CTC_ERROR_RETURN(_sys_at_serdes_speed_switch_proc(lchip, serdes_id, SERDES_SPEED_0G));
        }
    }
#endif

    /* 4. config datapath */
#ifdef PCS_ONLY
    uint16 dport        = 0;

    for (lsd_num = 0; lsd_num < target->lsd_num; lsd_num++)
    {
        if (CTC_E_NONE == sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_LSD, target->lsd_list[lsd_num],
                DMPS_DB_TYPE_PORT, NULL, &dport))
        {
            if (SYS_USW_IS_CPUMAC_PORT(DMPS_DB_PORT(dport).port_type))
            {
                continue;
            }

            CTC_ERROR_RETURN(sys_usw_dmps_db_get_dport_relative_id(lchip, dport, DMPS_DB_TYPE_CHAN, &chan_id));
            CTC_ERROR_RETURN(_sys_at_datapath_nettx_cfg(lchip, DMPS_DB_CHAN(chan_id).core_id,
                DMPS_DB_CHAN(chan_id).pp_id, DMPS_DB_CHAN(chan_id).dp_id, dport));
            CTC_ERROR_RETURN(_sys_at_datapath_netrx_cfg(lchip, DMPS_DB_CHAN(chan_id).core_id,
                DMPS_DB_CHAN(chan_id).pp_id, DMPS_DB_CHAN(chan_id).dp_id, dport));
        }
    }
#else
    CTC_ERROR_RETURN(_sys_at_datapath_dynamic_switch_dp(lchip, target, 0));
#endif

#ifdef PCS_ONLY
    /* 5. Update database: delete ralationship */
    for (lsd_num = 0; lsd_num < target->lsd_num; lsd_num++)
    {
        CTC_ERROR_RETURN(_sys_at_datapath_delete_relation(lchip, target->lsd_list[lsd_num]));
    }
#endif
    DP_DEBUG_FUNCTION_RETURN_PRINT();
    return CTC_E_NONE;
}

int32
_sys_at_datapath_mapping_cfg_from_none(uint8 lchip, uint16 lsd, ctc_chip_serdes_mode_t dst_mode, uint8 ovclk)
{
    uint8  serdes_num         = 0;
    uint8  idx                = 0;
    uint8  speed              = 0;
    uint8  if_type            = 0;
    uint8  fec_type           = 0;
    uint8  speed_mode         = 0;
    uint8  port_type          = 0;
    uint16 dport              = 0;
    uint16 mac_id             = 0;
    uint16 pcs_id             = 0;
    uint16 chan_id            = 0;
    uint16 psd                = 0;
    uint32 serdes_speed       = 0;
    uint32 support_speed      = 0;
    uint32 speed_value        = 0;
    sys_dmps_db_upt_info_t port_info  = {0};
    sys_dmps_db_upt_info_t upt_info_p = {0};
    sys_dmps_db_cpumac_map_t  p_map   = {0};

    SYS_AT_GET_SERDES_NUM_BY_MODE(dst_mode, serdes_num);

    if (0 == serdes_num)
    {
        return CTC_E_NONE;
    }

    idx = lsd % serdes_num;

    CTC_ERROR_RETURN(_sys_at_datapath_get_port_chan_by_serdes(lchip, lsd, &chan_id, &dport));
    if ((!sys_usw_dmps_db_is_usable_id(lchip, DMPS_DB_TYPE_PORT, dport))
        || (!sys_usw_dmps_db_is_usable_id(lchip, DMPS_DB_TYPE_CHAN, chan_id))
        || (!sys_usw_dmps_db_is_usable_id(lchip, DMPS_DB_TYPE_CHAN_RX, chan_id)))
    {
        return CTC_E_INVALID_PARAM;
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE, port_type);

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_cpumac_map(lchip, SYS_AT_GET_PORT_IDX(dport), &p_map));

    if (SYS_AT_IS_NW_SERDES(lsd))
    {
        port_type = SYS_DMPS_NETWORK_PORT;
    }
    else
    {
        port_type = p_map.is_network ? SYS_DMPS_CPUMAC_NETWORK_PORT : SYS_DMPS_CPU_MAC_PORT;
    }

    if (SYS_DMPS_CPU_MAC_PORT == port_type)
    {
        chan_id = SYS_AT_CHAN_CPUMAC_START + (lsd - SYS_AT_NW_SERDES_NUM);
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES, lsd);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_SUPPORT_SPEED);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_MAC_ID,        mac_id);
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_PCS_ID,        pcs_id);
    DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_PHYSIC_SERDES, psd);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_SUPPORT_SPEED, support_speed);

    if (SYS_DMPS_IS_PAM4_MODE(dst_mode))
    {
        fec_type = SYS_DMPS_FEC_TYPE_RS544;
    }
    else
    {
        fec_type = SYS_DMPS_FEC_TYPE_NONE;
    }

    if (0 == idx)
    {
        SYS_AT_GET_PORT_IFTYPE(dst_mode,  if_type);
        SYS_DMPS_GET_PORT_SPEED(dst_mode, speed_mode);
        SYS_USW_GET_SPEED_VALUE(speed_mode, fec_type, ovclk, speed_value);

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &upt_info_p));
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_DPORT,         dport);
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_CHAN_ID,       chan_id);
        DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_CHAN_RX_ID,    chan_id);
        DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_IF_MODE,       dst_mode);
        DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_TYPE,          port_type);
        DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_IF_TYPE,       if_type);
        DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_FEC_TYPE,      fec_type);
        DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_CHAN_SPEED_MODE,    speed_mode);
        DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_CHAN_RX_SPEED_MODE, speed_mode);
        DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_CHAN_SPEED_VALUE,   speed_value);
        DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_CHAN_RX_SPEED_VALUE,speed_value);
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &upt_info_p));
    }

    speed = sys_usw_dmps_get_speed_from_serdes_info(dst_mode, fec_type, ovclk);
    if (!((1 << speed) & support_speed))
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " %% Serdes %d cannot support this speed!  \n", psd);
        return CTC_E_INVALID_CONFIG;
    }
    SYS_USW_SERDES_SPEED_2_VALUE(speed, serdes_speed);

    if (idx != 0)
    {
        CTC_ERROR_RETURN(_sys_at_datapath_get_port_chan_by_serdes(lchip, (lsd-idx), &chan_id, &dport));
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &upt_info_p));
    DMPS_DB_SET_MAP_UPDATE(upt_info_p);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_MAC_ID,        mac_id);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_PCS_ID,        pcs_id);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_LOGIC_SERDES,  lsd);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_OLD_PHYSIC_SERDES, psd);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_DPORT,             dport);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_CHAN_ID,           chan_id);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_CHAN_RX_ID,        chan_id);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_MAC_ID,            mac_id  - idx);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_PCS_ID,            pcs_id  - idx);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_LOGIC_SERDES,      lsd);
    DMPS_DB_SET_MAP_INFO(upt_info_p, DMPS_DB_PHYSIC_SERDES,     psd);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_LSD_PCSL_IDX, idx);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PSD_OCS,      ovclk);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PSD_SPEED,    serdes_speed);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_IS_AN_FIRST,    0);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_LINK_FSM,   PMA_RX_NONREADY);
    DMPS_DB_SET_PROPERTY_INFO(upt_info_p, DMPS_DB_PORT_LINK_MODE,  g_port_link_mode);
    CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &upt_info_p));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_dynamic_switch_from_none(uint8 lchip, sys_dmps_ds_list_t* target, uint8 is_switch_serdes)
{
    uint8  lsd_num    = 0;
    uint8  dport_num  = 0;
    uint16 dport      = 0;
    uint16 mac_id     = 0;
    uint16 lsd        = target->lsd_list[0];
#ifdef PCS_ONLY
    uint8  chan_num   = 0;
    uint16 chan_id    = 0;
#endif

    if (CTC_CHIP_SERDES_NONE_MODE == target->dst_mode)
    {
        return CTC_E_NONE;
    }
    DP_DEBUG_FUNCTION_CALLED_PRINT();

    /* 1. Update database */
    for (lsd_num = 0; lsd_num < target->lsd_num; lsd_num++)
    {
        CTC_ERROR_RETURN(_sys_at_datapath_mapping_cfg_from_none(lchip, target->lsd_list[lsd_num], target->dst_mode, target->ovclk));
    }

    if (is_switch_serdes)
    {
        for(dport_num = 0; dport_num < target->dst_dport_num; dport_num++)
        {
            CTC_ERROR_RETURN(sys_at_mcu_add_port_mapping(lchip, target->dst_dport_list[dport_num]));
        }
    }
    
#if ((!defined(EMULATION_ENV) && (0 == SDK_WORK_PLATFORM)) || defined(AT_SERDES_SIM))
    if (is_switch_serdes)
    {
        uint16 psd          = 0;
        uint8  fec_type     = 0;
        uint32 serdes_speed = 0;
        /* 2. config serdes */
        for(lsd_num = 0; lsd_num < target->lsd_num; lsd_num++)
        {
            lsd = target->lsd_list[lsd_num];
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_LSD, lsd, DMPS_DB_TYPE_PSD, NULL, &psd));
            fec_type = SYS_DMPS_IS_PAM4_MODE(target->dst_mode) ? SYS_DMPS_FEC_TYPE_RS544 : SYS_DMPS_FEC_TYPE_NONE;
            serdes_speed = sys_usw_dmps_get_speed_from_serdes_info(target->dst_mode, fec_type, target->ovclk);
            CTC_ERROR_RETURN(_sys_at_serdes_speed_switch_proc(lchip, psd, serdes_speed));
        }
    }
#endif

    /* 3. config MAC/PCS/HATA register */
    for (dport_num = 0; dport_num < target->dst_dport_num; dport_num++)
    {
        dport = target->dst_dport_list[dport_num];
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, DMPS_DB_TYPE_MAC, NULL, &mac_id));
        if (SYS_AT_IS_NW_SERDES(lsd))
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_nw_config_by_mac_id(lchip, mac_id));
        }
        else
        {
#ifdef AT_CPUMAC
            CTC_ERROR_RETURN(_sys_at_cpumac_set_mac_config(lchip, mac_id));
#endif
        }
    }

    /* 4. config datapath */
#ifdef PCS_ONLY
    for (chan_num = 0; chan_num < target->chan_info.dst_chan_num; chan_num++)
    {
        chan_id = target->chan_info.dst_chan_list[chan_num];
        dport   = target->dst_dport_list[chan_num];

        
        if (SYS_USW_IS_CPUMAC_PORT(DMPS_DB_PORT(dport).port_type))
        {
            continue;
        }

        CTC_ERROR_RETURN(_sys_at_datapath_nettx_cfg(lchip, DMPS_DB_CHAN(chan_id).core_id,
            DMPS_DB_CHAN(chan_id).pp_id, DMPS_DB_CHAN(chan_id).dp_id, dport));
        CTC_ERROR_RETURN(_sys_at_datapath_netrx_cfg(lchip, DMPS_DB_CHAN(chan_id).core_id,
            DMPS_DB_CHAN(chan_id).pp_id, DMPS_DB_CHAN(chan_id).dp_id, dport));
    }
#else
    CTC_ERROR_RETURN(_sys_at_datapath_dynamic_switch_dp(lchip, target, 1));
#endif
    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

int32
_sys_at_datapath_dynamic_switch(uint8 lchip, sys_dmps_ds_list_t* target, uint8 is_switch_serdes)
{
    if (0 == target->lsd_num)
    {
        return CTC_E_NONE;
    }

    /* 1. switch to none */
    CTC_ERROR_RETURN(_sys_at_datapath_dynamic_switch_to_none(lchip, target, is_switch_serdes));

    /* 2. switch from none */
    CTC_ERROR_RETURN(_sys_at_datapath_dynamic_switch_from_none(lchip, target, is_switch_serdes));

    /* 3. if emu, config macshim */
#ifdef EMULATION_ENV
#ifndef EMULATOR_ENV
    uint8  mac_group_id = 0;
    mac_group_id = (target->lsd_list[0] / AT_SERDES_NUM_PER_MCMAC) % AT_MCMAC_NUM_PER_CORE;

#ifdef PCS_ONLY
    if ((0 == mac_group_id) || (1 == mac_group_id))
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_macshim_pre_group(lchip, mac_group_id));
    }
#else
    uint8  chip_type    = SYS_AT_GET_CHIP_TYPE(lchip);

    if (SYS_AT_IS_1PP(chip_type))
    {
        /* In 1pp Eemulation, group 18 and 19 have macshim */
        if ((18 == mac_group_id) || (19 == mac_group_id))
        {
            CTC_ERROR_RETURN(_sys_at_mac_set_macshim_pre_group(lchip, mac_group_id));
        }
    }
    else
    {
        CTC_ERROR_RETURN(_sys_at_mac_set_macshim_pre_group(lchip, mac_group_id));
    }
#endif
#endif
#endif
    return CTC_E_NONE;
}

/* check band-width in changing */
int32
_sys_at_datapath_check_bw(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 txqm_id, sys_dmps_change_chan_info_t* info, uint8 dir_bmp)
{
    uint8  speed_mode = 0;
    uint8  port_type  = 0;
    uint8  chan_num   = 0;
    uint16 dport      = 0;
    uint16 chan_id    = 0;
    uint16 st_chan    = 0;
    uint16 en_chan    = 0;
    uint16 txqm_bw    = 0;
    uint16 speed      = 0;
    uint16 chan_list[DMPS_MAX_NUM_PER_MODULE] = {0};
    sys_dmps_db_upt_info_t port_info  = {0};

    st_chan = core_id * AT_NW_CHAN_NUM_PER_CORE + pp_id * SYS_AT_NW_CHAN_NUM_PER_PP + dp_id * SYS_AT_NW_CHAN_NUM_PER_DP;
    en_chan = st_chan + SYS_AT_NW_CHAN_NUM_PER_DP;

    /* get txqm bw before changing */
    for (chan_id = st_chan; chan_id < en_chan; chan_id++)
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, GET_CHAN_ID_BY_DIR(dir_bmp), chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_SPEED_MODE_BY_DIR(dir_bmp));
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE, port_type);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SPEED_MODE_BY_DIR(dir_bmp), speed_mode);
        SYS_CONDITION_CONTINUE((!sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport))
            || (SYS_DMPS_NETWORK_PORT != port_type)
            || (!_sys_at_datapath_is_same_core_pp_dp_txqm(lchip, chan_id, core_id, pp_id, dp_id, txqm_id, dir_bmp)));

        CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, GET_CHAN_TYPE_BY_DIR(dir_bmp), &chan_num, chan_list));
        if (chan_id != chan_list[0])
        {
            continue;
        }

        SYS_DATAPATH_SYS_MODE_TO_SPEED(speed_mode, speed);
        txqm_bw += speed;
    }

    /* get txqm bw after changing */
    for (chan_num = 0; chan_num < info->src_chan_num; chan_num++)
    {
        chan_id = info->src_chan_list[chan_num];
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, GET_CHAN_ID_BY_DIR(dir_bmp), chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_SPEED_MODE_BY_DIR(dir_bmp));
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SPEED_MODE_BY_DIR(dir_bmp), speed_mode);
        SYS_DATAPATH_SYS_MODE_TO_SPEED(speed_mode, speed);
        txqm_bw -= speed;
    }

    SYS_DATAPATH_SYS_MODE_TO_SPEED(info->dst_speed_mode, speed);
    txqm_bw += (info->dst_chan_num * speed);

    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "%% After change, txqm bw is %d\n", txqm_bw);

    if (txqm_bw > 800)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% BW of core %d pp %d dp %d txqm %d is lager than 800G! \n",
            core_id, pp_id, dp_id, txqm_id);
        return CTC_E_INVALID_CONFIG;
    }

    return CTC_E_NONE;
}

/* check credit in changing */
int32
_sys_at_datapath_check_credit(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 txqm_id, sys_dmps_change_chan_info_t* info, uint8 dir_bmp)
{
    uint8  speed_mode = 0;
    uint8  port_type  = 0;
    uint8  mac_client = 0;
    uint8  prio_p     = 0;
    uint16 st_chan    = 0;
    uint16 en_chan    = 0;
    uint16 chan_id    = 0;
    uint16 chan_num   = 0;
    uint16 dport      = 0;
    uint16 speed      = 0;
    uint16 sub_chan   = 0;
    uint16 txqm_cli   = 0;
    uint16 credit     = 0;
    uint32 sum_qmgr   = 0;
    uint32 sum_brsop  = 0;
    uint32 sum_brbdy  = 0;
    uint32 sum_br_lo  = 0;
    uint32 sum_br_re  = 0;
    uint32 sum_epe    = 0;
    uint32 sum_nettx  = 0;
    uint16 txqm_speed[SYS_AT_MAC_CLIENT_PER_TXQM] = {0};    /* txqm speed list, without cpumac, misc, loop */
    uint16 dp_speed[SYS_AT_CHAN_NUM_PER_DP]       = {0};    /* dp   speed list, with    cpumac, misc, loop */
    uint8  prio[SYS_AT_CHAN_NUM_PER_DP]           = {0};    /* dp   prio list */
    sys_datapath_bufsz_step_t  step               = {0};
    sys_dmps_db_upt_info_t port_info              = {0};

    st_chan = core_id * AT_NW_CHAN_NUM_PER_CORE + pp_id * SYS_AT_NW_CHAN_NUM_PER_PP + dp_id * SYS_AT_NW_CHAN_NUM_PER_DP;
    en_chan = st_chan + SYS_AT_NW_CHAN_NUM_PER_DP;

    /* network chan: get speed list before change */
    for (chan_id = st_chan; chan_id < en_chan; chan_id++)
    {
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, GET_CHAN_TYPE_BY_DIR(dir_bmp), chan_id));

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, GET_CHAN_ID_BY_DIR(dir_bmp), chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_SPEED_MODE_BY_DIR(dir_bmp));
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp));
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp));
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_PRIO_BY_DIR(dir_bmp));
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SPEED_MODE_BY_DIR(dir_bmp),    speed_mode);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp),   sub_chan);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp), mac_client);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_PRIO_BY_DIR(dir_bmp),          prio_p);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,             port_type);

        SYS_DATAPATH_SYS_MODE_TO_SPEED(speed_mode, speed);
        dp_speed[sub_chan] = speed;
        prio[sub_chan]   = prio_p;

        SYS_CONDITION_CONTINUE((!sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport))
            || (SYS_DMPS_NETWORK_PORT != port_type)
            || (!_sys_at_datapath_is_same_core_pp_dp_txqm(lchip, chan_id, core_id, pp_id, dp_id, txqm_id, dir_bmp)));

        txqm_speed[mac_client % SYS_AT_MAC_CLIENT_PER_TXQM] = speed;
    }

    /* misc chan */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, dp_id, SYS_AT_MISC_CHAN_ID_IN_DP, &chan_id, dir_bmp));
    if (sys_usw_dmps_db_is_valid_id(lchip, GET_CHAN_TYPE_BY_DIR(dir_bmp), chan_id))
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, GET_CHAN_ID_BY_DIR(dir_bmp), chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_SPEED_MODE_BY_DIR(dir_bmp));
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_PRIO_BY_DIR(dir_bmp));
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SPEED_MODE_BY_DIR(dir_bmp),    speed_mode);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_PRIO_BY_DIR(dir_bmp),          prio_p);
        SYS_DATAPATH_SYS_MODE_TO_SPEED(speed_mode, speed);
        dp_speed[SYS_AT_MISC_CHAN_ID_IN_DP] = speed;
        prio[SYS_AT_MISC_CHAN_ID_IN_DP]   = prio_p;
    }

    /* loop chan */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, dp_id, SYS_AT_LOOP_CHAN_ID_IN_DP, &chan_id, dir_bmp));
    if (sys_usw_dmps_db_is_valid_id(lchip, GET_CHAN_TYPE_BY_DIR(dir_bmp), chan_id))
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, GET_CHAN_ID_BY_DIR(dir_bmp), chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_SPEED_MODE_BY_DIR(dir_bmp));
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_PRIO_BY_DIR(dir_bmp));
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SPEED_MODE_BY_DIR(dir_bmp),    speed_mode);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_PRIO_BY_DIR(dir_bmp),          prio_p);
        SYS_DATAPATH_SYS_MODE_TO_SPEED(speed_mode, speed);
        dp_speed[SYS_AT_LOOP_CHAN_ID_IN_DP] = speed;
        prio[SYS_AT_LOOP_CHAN_ID_IN_DP]   = prio_p;
    }

    /* clear speed of change channel */
    for (chan_num = 0; chan_num < info->src_chan_num; chan_num++)
    {
        chan_id = info->src_chan_list[chan_num];

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, GET_CHAN_ID_BY_DIR(dir_bmp), chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp));
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp));
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp),     sub_chan);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp),   mac_client);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE, port_type);

        dp_speed[sub_chan] = 0;

        SYS_CONDITION_CONTINUE((!sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport))
            || (SYS_DMPS_NETWORK_PORT != port_type));

        txqm_speed[mac_client % SYS_AT_MAC_CLIENT_PER_TXQM] = 0;
    }

    SYS_DATAPATH_SYS_MODE_TO_SPEED(info->dst_speed_mode, speed);

    /* add speed of new channel */
    for (chan_num = 0; chan_num < info->dst_chan_num; chan_num++)
    {
        chan_id = info->dst_chan_list[chan_num];

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, GET_CHAN_ID_BY_DIR(dir_bmp), chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp));
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp));
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp),     sub_chan);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp),   mac_client);
 
        dp_speed[sub_chan] = speed;

        if (sub_chan < SYS_AT_NW_CHAN_NUM_PER_DP)
        {
            txqm_speed[mac_client % SYS_AT_MAC_CLIENT_PER_TXQM] = speed;
        }
    }

    if (CHAN_DIR_IS_TX(dir_bmp))
    {
        /* get credit sum of qmgr, br */
        for (sub_chan = 0; sub_chan < SYS_AT_CHAN_NUM_PER_DP; sub_chan++)
        {
            credit = _sys_at_qmgr_speed_to_credit(lchip, dp_speed[sub_chan]);
            sum_qmgr += credit;

            _sys_at_datapath_bufretrv_get_credit(lchip, dp_speed[sub_chan], &step, prio[sub_chan]);
            sum_brsop += step.sop_buf_num;
            sum_brbdy += step.body_buf_num;
            sum_br_lo += step.br_credit_cfg;
            sum_br_re += step.br_credit_cfg_remote;
        }

        /* get credit sum of epe, netTx */
        for (txqm_cli = 0; txqm_cli < SYS_AT_MAC_CLIENT_PER_TXQM; txqm_cli++)
        {
            credit = _sys_at_datapath_epe_speed_to_credit(txqm_speed[txqm_cli]);
            sum_epe += credit;

            credit = _sys_at_nettx_speed_to_credit(lchip, txqm_speed[txqm_cli]);
            sum_nettx += credit;
        }

        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "%% After change, sum_qmgr is %d, sum_brsop is %d,\
        sum_brbdy is %d, sum_br_lo is %d, sum_br_re is %d, sum_epe is %d, sum_nettx is %d\n",
            sum_qmgr, sum_brsop, sum_brbdy, sum_br_lo, sum_br_re, sum_epe, sum_nettx);
        /*qmgr credit per dp sum check (640 per dp)*/
        if (sum_qmgr > AT_MAX_QMGR_CREDIT_PER_DP)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% QMgr credit mistake in changing! dp %u, sum is %d \n",
                dp_id, sum_qmgr);
            return CTC_E_INVALID_CONFIG;
        }
        /*bufretrv credit per dp sum check (sop: 1536 per dp, body: 512 per dp)*/
        if (sum_brsop > AT_MAX_BR_SOP_CREDIT_PER_DP)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% BufRetrv sop credit mistake in changing! dp %u, sum is %d \n",
                dp_id, sum_brsop);
            return CTC_E_INVALID_CONFIG;
        }
        if (sum_brbdy > AT_MAX_BR_BODY_CREDIT_PER_DP)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% BufRetrv body credit mistake in changing! dp %u, sum is %d \n",
                dp_id, sum_brbdy);
            return CTC_E_INVALID_CONFIG;
        }
        if (sum_br_lo > AT_MAX_BR_LOCAL_CREDIT_PER_DP)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% BufRetrv local buf credit mistake in changing! dp %u, sum is %d \n",
                dp_id, sum_br_lo);
            return CTC_E_INVALID_CONFIG;
        }
        if (sum_br_re > AT_MAX_BR_REMOTE_CREDIT_PER_DP)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% BufRetrv remote buf credit mistake in changing! dp %u, sum is %d \n",
                dp_id, sum_br_re);
            return CTC_E_INVALID_CONFIG;
        }
        /*epe credit sum check (320 per TXQM)*/
        if (sum_epe > AT_MAX_EPE_CREDIT_PER_TXQM)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Epe credit mistake in changing! dp %u, dp_txqm %u, sum is %d \n",
                dp_id, txqm_id, sum_epe);
            return CTC_E_INVALID_CONFIG;
        }
        /*nettx credit sum check (320 per TXQM)*/
        if (sum_nettx > AT_MAX_NETTX_CREDIT_PER_TXQM)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Nettx credit mistake in changing! dp %u, dp_txqm %u, sum is %d \n",
                dp_id, txqm_id, sum_nettx);
            return CTC_E_INVALID_CONFIG;
        }
    }

    return CTC_E_NONE;
}


/* check calendar in changing */
int32
_sys_at_datapath_check_calendar(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 txqm_id, sys_dmps_change_chan_info_t* info, uint8 dir_bmp)
{
    int32   ret        = CTC_E_NONE;
    uint8   error      = TRUE;
    uint8   sub_chan   = 0;
    uint8   mac_client = 0;
    uint16* cal        = NULL;
    uint16  walk_end   = 0;
    uint16  chan_id    = 0;
    uint16  chan_num   = 0;
    uint16  speed      = 0;
    sys_at_cal_info_collect_t* cal_info = NULL;
    sys_dmps_db_upt_info_t port_info    = {0};

    cal = (uint16*)mem_malloc(MEM_DMPS_MODULE, SYS_AT_MAX_CAL_LEN * sizeof(uint16));
    CTC_ERROR_GOTO((NULL == cal) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_1);
    sal_memset(cal, 0xff, SYS_AT_MAX_CAL_LEN * sizeof(uint16));

    cal_info = (sys_at_cal_info_collect_t*)mem_malloc(MEM_DMPS_MODULE,
        SYS_AT_CHAN_NUM_PER_PP * sizeof(sys_at_cal_info_collect_t));
    CTC_ERROR_GOTO((NULL == cal_info) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_2);

    if (CHAN_DIR_IS_TX(dir_bmp))
    {
        /* 1.  check Qmgr calendar, consider CPUMAC, Misc and Loop */
        /* 1.1 info collect */
        _sys_at_calendar_speed_info_collect(lchip, cal_info, core_id, pp_id, SYS_AT_USELESS_ID8, SYS_AT_USELESS_ID8, SYS_AT_QMGR_CAL);

        /* 1.2 update collect information */
        for (chan_num = 0; chan_num < info->src_chan_num; chan_num++)
        {
            chan_id = info->src_chan_list[chan_num];
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SUB_CHAN_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID,   sub_chan);
            cal_info[sub_chan + dp_id * SYS_AT_CHAN_NUM_PER_DP].speed = 0;
        }
        for (chan_num = 0; chan_num < info->dst_chan_num; chan_num++)
        {
            chan_id = info->dst_chan_list[chan_num];
            SYS_DATAPATH_SYS_MODE_TO_SPEED(info->dst_speed_mode, speed);
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SUB_CHAN_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID,   sub_chan);
            cal_info[sub_chan + dp_id * SYS_AT_CHAN_NUM_PER_DP].speed = speed;
        }

        /* 1.3 calender caculateion */
        ret = _sys_at_datapath_qmgr_common_calendar(lchip, core_id, pp_id, &error, &walk_end, cal, cal_info);

        /* 1.4 check calendar */
        if ((CTC_E_NONE != ret) || (SYS_AT_MAX_CAL_LEN <= walk_end))
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Calculation of Qmgr calendar error! core_id %d pp_id %d\n", 
                core_id, pp_id);
            ret = CTC_E_INVALID_CONFIG;
            goto RELEASE_PTR_RETURN_3;
        }
        sal_memset(cal, 0, SYS_AT_MAX_CAL_LEN * sizeof(uint16));

        /* 2.  check BufRetrv calendar, consider CPUMAC */
        /* 2.1 info collect */
        _sys_at_calendar_speed_info_collect(lchip, cal_info, core_id, pp_id, dp_id, SYS_AT_USELESS_ID8, SYS_AT_BR_CAL);

        /* 2.2 update collect information */
        for (chan_num = 0; chan_num < info->src_chan_num; chan_num++)
        {
            chan_id = info->src_chan_list[chan_num];
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SUB_CHAN_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID,   sub_chan);
            cal_info[sub_chan].speed = 0;
        }
        for (chan_num = 0; chan_num < info->dst_chan_num; chan_num++)
        {
            chan_id = info->dst_chan_list[chan_num];
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SUB_CHAN_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID,   sub_chan);
            SYS_DATAPATH_SYS_MODE_TO_SPEED(info->dst_speed_mode, speed);
            cal_info[sub_chan].speed = speed;
        }

        /* 2.3 calender caculateion */
        ret = _sys_at_datapath_calculate_general_calendar_parser(lchip, core_id, pp_id, dp_id, TRUE, cal, &walk_end, cal_info);

        /* 2.4 check calendar */
        if ((CTC_E_NONE != ret) || (SYS_AT_MAX_CAL_LEN <= walk_end))
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Calculation of BufRetrv calendar error! core %d pp %d dp %d\n", 
                core_id, pp_id, dp_id);
            ret = CTC_E_INVALID_CONFIG;
            goto RELEASE_PTR_RETURN_3;
        }
        sal_memset(cal, 0, SYS_AT_MAX_CAL_LEN * sizeof(uint16));

        /* 3.  check Epe calendar, consider CPUMAC */
        /* 3.1 info collect */
        _sys_at_calendar_speed_info_collect(lchip, cal_info, core_id, pp_id, dp_id, SYS_AT_USELESS_ID8, SYS_AT_EPE_CAL);

        /* 3.2 update collect information */
        for (chan_num = 0; chan_num < info->src_chan_num; chan_num++)
        {
            chan_id = info->src_chan_list[chan_num];
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID,   mac_client);
            cal_info[mac_client].speed = 0;
        }
        for (chan_num = 0; chan_num < info->dst_chan_num; chan_num++)
        {
            chan_id = info->dst_chan_list[chan_num];
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID,   mac_client);
            SYS_DATAPATH_SYS_MODE_TO_SPEED(info->dst_speed_mode, speed);
            cal_info[mac_client].speed = speed;
        }

        /* 3.3 calender caculateion */
        ret = _sys_at_datapath_calculate_general_calendar_parser(lchip, core_id, pp_id, dp_id, TRUE, cal, &walk_end, cal_info);

        /* 3.4 check calendar */
        if ((CTC_E_NONE != ret) || (SYS_AT_MAX_CAL_LEN <= walk_end))
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Calculation of Epe calendar error! core %d pp %d dp %d\n", 
                core_id, pp_id, dp_id);
            ret = CTC_E_INVALID_CONFIG;
            goto RELEASE_PTR_RETURN_3;
        }
        sal_memset(cal, 0, SYS_AT_MAX_CAL_LEN * sizeof(uint16));

        /* 4.  check NetTx calendar */
        /* cpumac is no need in nettx */
        if (txqm_id >= SYS_AT_TXQM_NUM_PER_DP)
        {
            ret = CTC_E_NONE;
            goto RELEASE_PTR_RETURN_3;
        }
        /* 4.1 info collect */
        _sys_at_calendar_speed_info_collect(lchip, cal_info, core_id, pp_id, dp_id, txqm_id, SYS_AT_NETTX_CAL);

        /* 4.2 update collect information */
        for (chan_num = 0; chan_num < info->src_chan_num; chan_num++)
        {
            chan_id = info->src_chan_list[chan_num];
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID,   mac_client);
            cal_info[mac_client].speed = 0;
        }
        for (chan_num = 0; chan_num < info->dst_chan_num; chan_num++)
        {
            chan_id = info->dst_chan_list[chan_num];
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID,   mac_client);
            SYS_DATAPATH_SYS_MODE_TO_SPEED(info->dst_speed_mode, speed);
            cal_info[mac_client].speed = speed;
        }

        /* 4.3 calender caculateion */
        ret = _sys_at_datapath_nettx_common_calendar(lchip, core_id, pp_id, dp_id, txqm_id, &error, &walk_end, cal, cal_info);

        /* 4.4 check calendar */
        if ((CTC_E_NONE != ret) || (AT_NETTX_CAL_ENTRY_PRT_TXQM <= walk_end))
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Calculation of NetTx calendar error! core %d pp %d dp %d txqm %d\n", 
                core_id, pp_id, dp_id, txqm_id);
            ret = CTC_E_INVALID_CONFIG;
            goto RELEASE_PTR_RETURN_3;
        }
    }

    if (CHAN_DIR_IS_RX(dir_bmp))
    {
        /* 5.  check NetRx calendar */
        /* 5.1 info collect */
        _sys_at_calendar_speed_info_collect(lchip, cal_info, core_id, pp_id, dp_id, SYS_AT_USELESS_ID8, SYS_AT_NETRX_CAL);
        /* 5.2 update collect information */
        for (chan_num = 0; chan_num < info->src_chan_num; chan_num++)
        {
            chan_id = info->src_chan_list[chan_num];
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_RX_ID, chan_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_RX_MAC_CLIENT_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_MAC_CLIENT_ID,   mac_client);
            cal_info[mac_client].speed = 0;
        }
        for (chan_num = 0; chan_num < info->dst_chan_num; chan_num++)
        {
            chan_id = info->dst_chan_list[chan_num];
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_RX_ID, chan_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_RX_MAC_CLIENT_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_MAC_CLIENT_ID,   mac_client);
            SYS_DATAPATH_SYS_MODE_TO_SPEED(info->dst_speed_mode, speed);
            cal_info[mac_client].speed = speed;
        }

        /* 5.3 calender caculateion */
        ret = _sys_at_datapath_calculate_general_calendar_parser(lchip, core_id, pp_id, dp_id, FALSE, cal, &walk_end, cal_info);

        /* 5.4 check calendar */
        if ((CTC_E_NONE != ret) || (SYS_AT_MAX_CAL_LEN <= walk_end))
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Calculation of NetRx calendar error! core %d pp %d dp %d\n", 
                core_id, pp_id, dp_id);
            ret = CTC_E_INVALID_CONFIG;
            goto RELEASE_PTR_RETURN_3;
        }
        sal_memset(cal, 0, SYS_AT_MAX_CAL_LEN * sizeof(uint16));
    }

RELEASE_PTR_RETURN_3:
    mem_free(cal_info);
RELEASE_PTR_RETURN_2:
    mem_free(cal);
RELEASE_PTR_RETURN_1:
    return ret;
}

/* check the validity of datapath */
int32
_sys_at_datapath_check(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 txqm_id, sys_dmps_change_chan_info_t* info, uint8 dir_bmp, uint8 check_bw)
{
#if ((1 == SDK_WORK_PLATFORM) || defined(EMULATOR_ENV) || (SDB_MEM_MODEL == SDB_MODE))
    return CTC_E_NONE;
#endif

    if (CHAN_DIR_IS_TX(dir_bmp))
    {
        if (check_bw)
        {
            /* 1. check band-width */
            CTC_ERROR_RETURN(_sys_at_datapath_check_bw(lchip, core_id, pp_id, dp_id, txqm_id, info, CHAN_DIR_TX));
        }

        /* 2. check credit */
        CTC_ERROR_RETURN(_sys_at_datapath_check_credit(lchip, core_id, pp_id, dp_id, txqm_id, info, CHAN_DIR_TX));

        /* 3. check calendar */
        CTC_ERROR_RETURN(_sys_at_datapath_check_calendar(lchip, core_id, pp_id, dp_id, txqm_id, info, CHAN_DIR_TX));
    }

    if (CHAN_DIR_IS_RX(dir_bmp))
    {
        if (check_bw)
        {
            /* 1. check band-width */
            CTC_ERROR_RETURN(_sys_at_datapath_check_bw(lchip, core_id, pp_id, dp_id, txqm_id, info, CHAN_DIR_RX));
        }

        /* 2. check credit */
        CTC_ERROR_RETURN(_sys_at_datapath_check_credit(lchip, core_id, pp_id, dp_id, txqm_id, info, CHAN_DIR_RX));

        /* 3. check calendar */
        CTC_ERROR_RETURN(_sys_at_datapath_check_calendar(lchip, core_id, pp_id, dp_id, txqm_id, info, CHAN_DIR_RX));
    }

    
    return CTC_E_NONE;
}

/* check the validity of dynamic switch */
int32
_sys_at_datapath_dynamic_switch_check(uint8 lchip, sys_dmps_ds_list_t* target)
{
    uint8  core_id = 0;
    uint8  pp_id   = 0;
    uint8  dp_id   = 0;
    uint8  txqm_id = 0;
    uint16 chan_id = 0;
    sys_dmps_db_upt_info_t port_info  = {0};

    if (0 == target->chan_info.dst_chan_num)
    {
        return CTC_E_NONE;
    }

    chan_id = target->chan_info.dst_chan_list[0];
    SYS_CONDITION_RETURN((!sys_usw_dmps_db_is_usable_id(lchip, DMPS_DB_TYPE_CHAN, chan_id)), CTC_E_INVALID_CONFIG);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_PP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_DP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_TXQM_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_PP_ID,   pp_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_DP_ID,   dp_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_TXQM_ID, txqm_id);

    if (SYS_AT_USELESS_ID8 != txqm_id)
    {
        CTC_ERROR_RETURN(_sys_at_datapath_check(lchip, core_id, pp_id, dp_id, txqm_id, &(target->chan_info), CHAN_DIR_TXRX, TRUE));
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_get_free_chan(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 txqm_id,
                                uint8 free_num, uint16* free_chan, uint16* free_sub_chan, uint16* free_mac_client, uint8 dir_bmp)
{
    uint8  cnt        = 0;
    uint8  free_id    = 0;
    uint8  is_rsv     = 0;
    uint16 p_sub_chan = SYS_AT_USELESS_ID16;
    uint16 p_mac_cli  = SYS_AT_USELESS_ID16;
    uint16 p_chan     = SYS_AT_USELESS_ID16;
    uint16 start_chan = 0;
    uint16 end_chan   = 0;
    uint16 chan_temp  = 0;
    uint8  chan_used[AT_CHAN_NUM_PER_DP_NW]            = {0};
    uint8  mac_client_used[SYS_AT_MAC_CLIENT_PER_TXQM] = {0};
    sys_dmps_db_upt_info_t port_info                   = {0};

    start_chan = core_id * AT_NW_CHAN_NUM_PER_CORE + pp_id * SYS_AT_NW_CHAN_NUM_PER_PP + dp_id * SYS_AT_NW_CHAN_NUM_PER_DP;
    end_chan   = start_chan + SYS_AT_NW_CHAN_NUM_PER_DP;

    /* traverse all channels in the same dp */
    for (chan_temp = start_chan; chan_temp < end_chan; chan_temp++)
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, GET_CHAN_ID_BY_DIR(dir_bmp), chan_temp);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_IS_RSV_BY_DIR(dir_bmp));
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_IS_RSV_BY_DIR(dir_bmp), is_rsv);

        SYS_CONDITION_CONTINUE((!sys_usw_dmps_db_is_valid_id(lchip, GET_CHAN_TYPE_BY_DIR(dir_bmp), chan_temp)) && (!is_rsv));

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, GET_CHAN_ID_BY_DIR(dir_bmp), chan_temp);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp));
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp));
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp),   p_sub_chan);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp), p_mac_cli);

        if (_sys_at_datapath_is_same_core_pp_dp_txqm(lchip, chan_temp, core_id, pp_id, dp_id, DMPS_INVALID_VALUE_U8, dir_bmp))
        {
            chan_used[p_sub_chan] = TRUE;
        }

        if (_sys_at_datapath_is_same_core_pp_dp_txqm(lchip, chan_temp, core_id, pp_id, dp_id, txqm_id, dir_bmp))
        {
            mac_client_used[p_mac_cli % SYS_AT_MAC_CLIENT_PER_TXQM] = TRUE;
        }
    }

    for (free_id = 0; free_id < free_num; free_id++)
    {
        p_sub_chan = SYS_AT_USELESS_ID16;
        p_mac_cli  = SYS_AT_USELESS_ID16;
        p_chan     = SYS_AT_USELESS_ID16;
        /* select free chan in the same dp */
        for (cnt = 0; cnt < AT_CHAN_NUM_PER_DP_NW; cnt++)
        {
            if (!chan_used[cnt])
            {
                p_sub_chan = cnt;
                chan_used[cnt] = TRUE;
                break;
            }
        }

        /* select free mac_client in the same txqm */
        for (cnt = 0; cnt < SYS_AT_MAC_CLIENT_PER_TXQM; cnt++)
        {
            if (!mac_client_used[cnt])
            {
                p_mac_cli = cnt + txqm_id * SYS_AT_MAC_CLIENT_PER_TXQM;
                mac_client_used[cnt] = TRUE;
                break;
            }
        }

        if ((SYS_AT_USELESS_ID16 == p_sub_chan) || (SYS_AT_USELESS_ID16 == p_mac_cli))
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% There is no free channel! \n");
            return CTC_E_NO_RESOURCE;
        }

        /* config free chan */
        p_chan = start_chan + p_sub_chan;
        SYS_USW_VALID_PTR_WRITE(free_chan + free_id, p_chan);
        SYS_USW_VALID_PTR_WRITE(free_sub_chan + free_id, p_sub_chan);
        SYS_USW_VALID_PTR_WRITE(free_mac_client + free_id, p_mac_cli);
    }

    return CTC_E_NONE;
}

uint8
sys_at_datapath_get_chip_type(uint8 lchip)
{
/* simulation or emulation */
#if (SDK_WORK_PLATFORM == 1)  || defined(EMULATION_ENV)
#ifdef EMULATOR_ENV
    return DRV_CHIP_SUB_TYPE_3;
#elif(1 == SDK_WORK_PLATFORM || (SDB_MEM_MODEL == SDB_MODE))
    return DRV_CHIP_SUB_TYPE_3;
#elif defined(DMPS_1PP0)
    return SYS_AT_SUBTYPE_1PP;
#else
    return DRV_CHIP_SUB_TYPE_1;
#endif

/* Demo */
#else
    return DRV_CHIP_SUB_TYPE(lchip);
    /*  DRV_CHIP_SUB_TYPE_1: CTC9260
        DRV_CHIP_SUB_TYPE_2: CTC9262
        DRV_CHIP_SUB_TYPE_3: CTC9280
        DRV_CHIP_SUB_TYPE_4: CTC9282  */
#endif
}

uint32
sys_at_datapath_dic_by_chip_type(uint8 lchip, const sys_at_dmps_id_dictionary_t** p_dic_pointer)
{
    uint8 chip_type = SYS_AT_GET_CHIP_TYPE(lchip);
    SYS_AT_GET_DIC_BY_CHIP_TYPE(chip_type, *p_dic_pointer);

    return CTC_E_NONE;
}


uint8
sys_at_datapath_chip_is_dc(uint8 lchip)
{
    uint8 chip_type = SYS_AT_GET_CHIP_TYPE(lchip);

    if ((DRV_CHIP_SUB_TYPE_3 == chip_type)
        || (DRV_CHIP_SUB_TYPE_4 == chip_type))
    {
        return TRUE;
    }

    return FALSE;
}

int32
_sys_at_datapath_get_misc_loop_chan(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint16 sub_chan_id, uint16* chan_id, uint8 dir_bmp)
{
    uint16 p_chan     = 0;
    uint16 p_sub_chan = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    if (SYS_AT_MISC_CHAN_ID_IN_DP == sub_chan_id)
    {
        for (p_chan = SYS_AT_CHAN_CPUMAC_NETWORK_START; p_chan <= SYS_AT_CHAN_CPUMAC_NETWORK_END; p_chan++)
        {
            SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, GET_CHAN_TYPE_BY_DIR(dir_bmp), p_chan));
            if (_sys_at_datapath_is_same_core_pp_dp_txqm(lchip, p_chan, core_id, pp_id, dp_id, DMPS_INVALID_VALUE_U8, dir_bmp))
            {
                CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
                DMPS_DB_SET_MAP_INFO(port_info, GET_CHAN_ID_BY_DIR(dir_bmp), p_chan);
                DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp));
                CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
                DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp), p_sub_chan);

                if (sub_chan_id == p_sub_chan)
                {
                    SYS_USW_VALID_PTR_WRITE(chan_id,  p_chan);
                    return CTC_E_NONE;
                }
            }
        }
    }

    for (p_chan = SYS_AT_CHAN_EUNIT_START; p_chan < SYS_AT_MAX_CHAN_NUM; p_chan++)
    {
         SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, GET_CHAN_TYPE_BY_DIR(dir_bmp), p_chan));
        if (_sys_at_datapath_is_same_core_pp_dp_txqm(lchip, p_chan, core_id, pp_id, dp_id, DMPS_INVALID_VALUE_U8, dir_bmp))
        {
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, GET_CHAN_ID_BY_DIR(dir_bmp), p_chan);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp));
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp), p_sub_chan);

            if (sub_chan_id == p_sub_chan)
            {
                SYS_USW_VALID_PTR_WRITE(chan_id,  p_chan);
                return CTC_E_NONE;
            }
        }
    }

    SYS_USW_VALID_PTR_WRITE(chan_id,  DMPS_INVALID_VALUE_U16);
    return CTC_E_NONE;
}

int32
_sys_at_datapath_get_dp_chan(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint16* chan_list, uint8 dir_bmp)
{
    uint8  chan_idx      = 0;
    uint16 start_chan    = 0;
    uint16 chan_id       = 0;

    start_chan = core_id * AT_NW_CHAN_NUM_PER_CORE + pp_id * SYS_AT_NW_CHAN_NUM_PER_PP + dp_id * SYS_AT_NW_CHAN_NUM_PER_DP;

    for (chan_idx = 0; chan_idx < SYS_AT_NW_CHAN_NUM_PER_DP; chan_idx++)
    {
        chan_list[chan_idx] = start_chan + chan_idx;
    }

    /* misc chan */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, dp_id, SYS_AT_MISC_CHAN_ID_IN_DP, &chan_id, dir_bmp));
    chan_list[SYS_AT_MISC_CHAN_ID_IN_DP] = chan_id;

    /* loop chan */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, dp_id, SYS_AT_LOOP_CHAN_ID_IN_DP, &chan_id, dir_bmp));
    chan_list[SYS_AT_LOOP_CHAN_ID_IN_DP] = chan_id;

    return CTC_E_NONE;
}

uint8 
_sys_at_datapath_get_serdes_type(uint16 logic_serdes_dc)
{
    uint16 logic_serdes_sc = SYS_AT_GET_SERDES_PER_CORE(logic_serdes_dc);
    uint8  ip_type   = 0;

    if(logic_serdes_sc >= SYS_AT_112G_SERDES_FIRST && logic_serdes_sc <= SYS_AT_112G_SERDES_LAST) /*hss 4-35*/
    {
        ip_type = SYS_AT_SERDES_112G;
    }
    else 
    {
        ip_type = SYS_AT_SERDES_56G;
    }
    
    return ip_type;
}

uint8
_sys_at_datapath_serdes_scale(uint8 lchip)
{
    uint8 serdes_scale = 0;
    (void) sys_usw_dmps_db_get_serdes_scale((lchip), &serdes_scale);
    return serdes_scale;
}

uint32
_sys_at_datapath_get_serdes_support_speed_bmp(uint8 lchip, uint8 chip_type, uint16 logic_serdes_dc)
{
    uint16 logic_serdes_sc = SYS_AT_GET_SERDES_PER_CORE(logic_serdes_dc);
    uint16 core_pll        = 0;

    /*CPUMAC*/
    if(logic_serdes_dc >= SYS_AT_NW_SERDES_NUM)
    {
        return AT_CPUMAC_SERDES_SUPPORT_SPEED;
    }

    if (chip_type == SYS_AT_SUBTYPE_1PP)
    {
        return AT_112G_SERDES_SUPPORT_SPEED_HIGH;
    }

    if ((logic_serdes_sc < SYS_AT_112G_SERDES_FIRST) || (logic_serdes_sc > SYS_AT_112G_SERDES_LAST))
    {
        return AT_56G_SERDES_SUPPORT_SPEED;
    }

    /*NW*/
    /* 900M: Network port donnot support mode of 100G per lane */
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1));
    if (900 == core_pll)
    {
        return AT_112G_SERDES_SUPPORT_SPEED_LOW;
    }

    switch(chip_type)
    {
        case DRV_CHIP_SUB_TYPE_1:
            if (AT_CHIP_IS_SERDES_AG_LOW(lchip))
            {
                return (((SYS_AT_SUPPORT_112G_FIRST <= logic_serdes_sc) && (SYS_AT_SUPPORT_112G_LAST >= logic_serdes_sc)) ?
                        AT_112G_SERDES_SUPPORT_SPEED_HIGH : AT_112G_SERDES_SUPPORT_SPEED_LOW);
            }
            else if (AT_CHIP_IS_SERDES_AG_HIGH(lchip))
            {
                return ((((24 <= logic_serdes_sc) && (71 >= logic_serdes_sc)) || ((88 <= logic_serdes_sc) && (135 >= logic_serdes_sc))) ?
                        AT_112G_SERDES_SUPPORT_SPEED_HIGH : AT_112G_SERDES_SUPPORT_SPEED_LOW);
            }
            else if ((AT_CHIP_IS_SERDES_PG_LOW(lchip)) || (AT_CHIP_IS_SERDES_PG_HIGH(lchip)))
            {
                return AT_112G_SERDES_SUPPORT_SPEED_HIGH;
            }
            else
            {
                return 0;
            }
        case DRV_CHIP_SUB_TYPE_3:
            return AT_112G_SERDES_SUPPORT_SPEED_HIGH;
        case DRV_CHIP_SUB_TYPE_2:
        case DRV_CHIP_SUB_TYPE_4:
            return AT_112G_SERDES_SUPPORT_SPEED_LOW;
        default:
            return 0;
    }
}

int32
_sys_at_datapath_init_mac_group(uint8 lchip)
{
    uint8 chip_type = SYS_AT_GET_CHIP_TYPE(lchip);
    uint8 core      = 0;
    uint32* p_mac_group_valid = NULL;
    uint32 mac_group_dcm_ag[DMPS_MAX_CORE_NUM] = {0x3fffc, 0x3fffc};
    uint32 mac_group_1pp[DMPS_MAX_CORE_NUM]    = {0xf0000, 0x0};

#ifdef EMULATION_ENV
#ifdef EMULATOR_ENV
    /* EMULATOR */
    uint32 mac_group_scm_ag_full[DMPS_MAX_CORE_NUM] = {0xfffff, 0};
    uint32 mac_group_scm_ag[DMPS_MAX_CORE_NUM]      = {0x3fffc, 0};
    uint32 mac_group_scm_pg[DMPS_MAX_CORE_NUM]      = {0x7fec0, 0};
    uint32 mac_group_dcm_pg[DMPS_MAX_CORE_NUM]      = {0x34800, 0x34800};
#else
#ifdef PCS_ONLY
    /* PCS_ONLY */
    uint32 mac_group_scm_ag_full[DMPS_MAX_CORE_NUM] = {0xfea80, 0};
    uint32 mac_group_scm_ag[DMPS_MAX_CORE_NUM]      = {0xf,     0};
    uint32 mac_group_scm_pg[DMPS_MAX_CORE_NUM]      = {0x7fec0, 0};
    uint32 mac_group_dcm_pg[DMPS_MAX_CORE_NUM]      = {0x39f9c, 0x39f9c};
#else
    /* EMULATION */
    uint32 mac_group_scm_ag_full[DMPS_MAX_CORE_NUM] = {0xfea80, 0};
    uint32 mac_group_scm_ag[DMPS_MAX_CORE_NUM]      = {0x3ec80, 0};
    uint32 mac_group_scm_pg[DMPS_MAX_CORE_NUM]      = {0x7fec0, 0};
    uint32 mac_group_dcm_pg[DMPS_MAX_CORE_NUM]      = {0x39f9c, 0x39f9c};
#endif
#endif
#else
    /* DEMO */
    uint32 mac_group_scm_ag_full[DMPS_MAX_CORE_NUM] = {0xfffff, 0};
    uint32 mac_group_scm_ag[DMPS_MAX_CORE_NUM]      = {0x3fffc, 0};
    uint32 mac_group_scm_pg[DMPS_MAX_CORE_NUM]      = {0x7fffe, 0};
    uint32 mac_group_dcm_pg[DMPS_MAX_CORE_NUM]      = {0x3fffc, 0x3fffc};
#endif

    switch (chip_type)
    {
        case DRV_CHIP_SUB_TYPE_1:
            if (AT_CHIP_IS_SERDES_AG(lchip))
            {
                p_mac_group_valid = mac_group_scm_ag_full;
            }
            else if (AT_CHIP_IS_SERDES_PG_LOW(lchip))
            {
                p_mac_group_valid = mac_group_scm_pg;
            }
            else if (AT_CHIP_IS_SERDES_PG_HIGH(lchip))
            {
                p_mac_group_valid = mac_group_scm_ag;
            }
            break;
        case DRV_CHIP_SUB_TYPE_2:
            p_mac_group_valid = mac_group_scm_pg;
            break;
        case DRV_CHIP_SUB_TYPE_3:
            p_mac_group_valid = mac_group_dcm_ag;
            break;
        case DRV_CHIP_SUB_TYPE_4:
            p_mac_group_valid = mac_group_dcm_pg;
            break;
        case SYS_AT_SUBTYPE_1PP:
            p_mac_group_valid = mac_group_1pp;
            break;
        default:
            return CTC_E_INVALID_CONFIG;
    }

    for(core = 0; core < DMPS_MAX_CORE_NUM; core++)
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_mac_group_valid(lchip, core, p_mac_group_valid[core]));
    }

    return CTC_E_NONE;
}

static uint8 sys_at_datapath_init_get_stack_en(ctc_datapath_global_cfg_t* p_cfg)
{
    uint16 logic_serdes = 0;
    uint8 stack_enable = 1;

    for(logic_serdes = 0; logic_serdes < CTC_DATAPATH_SERDES_NUM; logic_serdes++)
    {
        /* serdes flag bit0 set means stack is enabled */
        if (SYS_AT_BMP_IS_SET(p_cfg->serdes[logic_serdes].flag, CTC_DATAPATH_SERDES_FLAG_LPORT_VALID))
        {
            break;
        }
    }

    if (CTC_DATAPATH_SERDES_NUM == logic_serdes)
    {
        stack_enable = 0;
    }

    return stack_enable;
}

static int32
sys_at_datapath_init_priority_lport_calculation(uint8 lchip, ctc_datapath_global_cfg_t* p_cfg, const sys_at_dmps_id_dictionary_t* p_dict,
                                                uint16 nw_lsd_num, uint16* low_prio_port_start)
{
    uint8  lane_num           = 0;
    uint8  core_id            = 0;
    uint8  mac_group_id       = 0;
    uint16 logic_serdes_dc    = 0; /*logic serdes dual-core (0~319)*/
    uint16 logic_serdes_sc    = 0; /*logic serdes single-core (0~159)*/
    uint16 chan_idx           = 0;
    uint8  occupy_flag        = 0;
    uint16 nw_prio_port_cnt   = 0;
    ctc_datapath_serdes_prop_t*     p_serdes_cfg = NULL;

    for(logic_serdes_dc = 0; logic_serdes_dc < nw_lsd_num; logic_serdes_dc++)
    {
        mac_group_id = logic_serdes_dc / AT_SERDES_NUM_PER_MCMAC % AT_MCMAC_NUM_PER_CORE;
        if (!SYS_AT_MAC_GROUP_IS_VAILD(lchip, core_id, mac_group_id))
        {
            continue;
        }

        p_serdes_cfg = &(p_cfg->serdes[logic_serdes_dc]);
        SYS_CONDITION_CONTINUE(NULL == p_serdes_cfg);

        /*if serdes no need to alloc chan & lport, skip*/
        SYS_CONDITION_CONTINUE(SYS_DMPS_INVALID_U16 == p_serdes_cfg->physical_serdes_id);
        if(SYS_SERDES_DYN_FORBID_ALL == p_serdes_cfg->is_dynamic)
        {
            SYS_AT_GET_LANE_NUM_BY_MODE(p_serdes_cfg->mode, lane_num);
            SYS_CONDITION_CONTINUE(0 == lane_num);
            SYS_CONDITION_CONTINUE(0 != logic_serdes_dc % lane_num);
        }

        core_id         = SYS_AT_GET_CORE_ID_BY_LOGIC_SERDES(logic_serdes_dc);
        logic_serdes_sc = logic_serdes_dc % DMPS_MAX_SERDES_NUM_PER_CORE;
        chan_idx = p_dict[logic_serdes_sc].pp_id * SYS_AT_NW_CHAN_NUM_PER_PP +
                  (p_dict[logic_serdes_sc].dp_id % SYS_AT_DP_NUM_PER_PP) * SYS_AT_NW_CHAN_NUM_PER_DP +
                   p_dict[logic_serdes_sc].sub_chan;

        /*if chan_idx is out of bound || the slot is not empty, skip*/
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan2lsd(lchip, core_id, chan_idx, &occupy_flag, NULL, NULL));
        SYS_CONDITION_CONTINUE(SYS_DP_CHAN_LPORT_OCCUPY_RSV != occupy_flag);

        if (FALSE == SYS_AT_BMP_IS_SET(p_serdes_cfg->flag, CTC_DATAPATH_SERDES_FLAG_LPORT_VALID))
        {
            nw_prio_port_cnt++;
        }
    }

    if (nw_prio_port_cnt >= SYS_SPECIAL_RSV_PORT_START)
    {
        nw_prio_port_cnt += SYS_SPECIAL_RSV_PORT_NUM;
    }
    *low_prio_port_start = nw_prio_port_cnt;

    return CTC_E_NONE;
}


int32
_sys_at_datapath_init_chan_2_logic_serdes_map(uint8 lchip, ctc_datapath_global_cfg_t* p_cfg)
{
    uint8  lane_num           = 0;
    uint8  core_id            = 0;
    uint8  core_num           = 0;
    uint8  mac_group_id       = 0;
    uint8  chip_type          = 0;
    uint16 logic_serdes_dc    = 0; /*logic serdes dual-core (0~319)*/
    uint16 logic_serdes_sc    = 0; /*logic serdes single-core (0~159)*/
    uint16 nw_lsd_num         = 0;
    uint16 chan_idx           = 0;
    uint16 lport              = 0;
    uint16 dport              = 0;
    uint16 inferior_port      = 0;
    uint16 high_prio_port     = 0;
    uint8  occupy_flag        = 0;
    uint8  bpe_full_mode      = 0;
    uint8  stack_en           = 0;
    sys_dmps_db_upt_info_t port_info                = {0};
    const sys_at_dmps_id_dictionary_t* p_dictionary = NULL;
    ctc_datapath_serdes_prop_t*        p_serdes_cfg = NULL;

    chip_type = SYS_AT_GET_CHIP_TYPE(lchip);

    /*determine which subtype dictionary to use*/
    SYS_AT_GET_DIC_BY_CHIP_TYPE(chip_type, p_dictionary);
    if (NULL == p_dictionary)
    {
        return CTC_E_INVALID_CONFIG;
    }

    core_num   = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;
    nw_lsd_num = DMPS_MAX_SERDES_NUM_PER_CORE * core_num;

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_bpe_full_mode(lchip, &bpe_full_mode));

    stack_en = sys_at_datapath_init_get_stack_en(p_cfg);
    if (stack_en)
    {
        CTC_ERROR_RETURN(sys_at_datapath_init_priority_lport_calculation(lchip, p_cfg, p_dictionary, nw_lsd_num, &inferior_port));
    }

    for(logic_serdes_dc = 0; logic_serdes_dc < nw_lsd_num; logic_serdes_dc++)
    {
        mac_group_id = logic_serdes_dc / AT_SERDES_NUM_PER_MCMAC % AT_MCMAC_NUM_PER_CORE;
        if (!SYS_AT_MAC_GROUP_IS_VAILD(lchip, core_id, mac_group_id))
        {
            continue;
        }

        p_serdes_cfg = &(p_cfg->serdes[logic_serdes_dc]);
        SYS_CONDITION_CONTINUE(NULL == p_serdes_cfg);

        /*if serdes no need to alloc chan & lport, skip*/
        SYS_CONDITION_CONTINUE(SYS_DMPS_INVALID_U16 == p_serdes_cfg->physical_serdes_id);
        if(SYS_SERDES_DYN_FORBID_ALL == p_serdes_cfg->is_dynamic)
        {
            SYS_AT_GET_LANE_NUM_BY_MODE(p_serdes_cfg->mode, lane_num);
            SYS_CONDITION_CONTINUE(0 == lane_num);
            SYS_CONDITION_CONTINUE(0 != logic_serdes_dc % lane_num);
        }

        core_id         = SYS_AT_GET_CORE_ID_BY_LOGIC_SERDES(logic_serdes_dc);
        logic_serdes_sc = logic_serdes_dc % DMPS_MAX_SERDES_NUM_PER_CORE;
        chan_idx = p_dictionary[logic_serdes_sc].pp_id * SYS_AT_NW_CHAN_NUM_PER_PP +
                    (p_dictionary[logic_serdes_sc].dp_id % SYS_AT_DP_NUM_PER_PP) * SYS_AT_NW_CHAN_NUM_PER_DP +
                    p_dictionary[logic_serdes_sc].sub_chan;

        /*if chan_idx is out of bound || the slot is not empty, skip*/
        //SYS_CONDITION_CONTINUE(AT_CHAN_NUM_PER_CORE <= chan_idx);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan2lsd(lchip, core_id, chan_idx, &occupy_flag, NULL, NULL));
        SYS_CONDITION_CONTINUE(SYS_DP_CHAN_LPORT_OCCUPY_RSV != occupy_flag);

        /*different priority lports use different start port id*/
        dport = ((stack_en) && (!SYS_AT_BMP_IS_SET(p_serdes_cfg->flag, CTC_DATAPATH_SERDES_FLAG_LPORT_VALID))) ? high_prio_port : inferior_port;
        lport = dport;

        /*alloc new chan in g_chan_2_logic_serdes_map*/
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_chan2lsd(lchip, core_id, chan_idx, 
            SYS_DP_CHAN_LPORT_OCCUPY_IN_USE, logic_serdes_dc, dport));

        if (!bpe_full_mode)
        {
            /*init lport-dport map*/
            CTC_ERROR_RETURN(sys_usw_dmps_db_set_ext_lport_map(lchip, lport, dport));
        }

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                      dport);
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID,                    SYS_AT_GET_CHAN_ID_BY_CORE(core_id, chan_idx));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_RX_ID,                 SYS_AT_GET_CHAN_ID_BY_CORE(core_id, chan_idx));
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,             SYS_DMPS_NETWORK_PORT);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IS_RSV,           TRUE);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,          core_id);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_PP_ID,            p_dictionary[logic_serdes_sc].pp_id);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_DP_ID,            p_dictionary[logic_serdes_sc].dp_id % AT_DP_NUM_PER_PP);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_TXQM_ID,          p_dictionary[logic_serdes_sc].txqm_id);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID,    p_dictionary[logic_serdes_sc].mac_client % SYS_AT_NW_MAC_CLIENT_PER_DP);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID,      p_dictionary[logic_serdes_sc].sub_chan);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_PRIO,             0);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_IS_RSV,           TRUE);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_CORE_ID,       core_id);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_PP_ID,         p_dictionary[logic_serdes_sc].pp_id);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_DP_ID,         p_dictionary[logic_serdes_sc].dp_id % AT_DP_NUM_PER_PP);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_TXQM_ID,       p_dictionary[logic_serdes_sc].txqm_id);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_MAC_CLIENT_ID, p_dictionary[logic_serdes_sc].mac_client % SYS_AT_NW_MAC_CLIENT_PER_DP);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_SUB_CHAN_ID,   p_dictionary[logic_serdes_sc].sub_chan);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_PRIO,          0);
        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_IS_RSV,        TRUE);
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &port_info));

        /* opf: Assign channel and port */
        CTC_ERROR_RETURN(sys_usw_dmps_db_assign_chan(lchip, SYS_AT_GET_CHAN_ID_BY_CORE(core_id, chan_idx)));
        CTC_ERROR_RETURN(sys_usw_dmps_db_assign_port(lchip, lport));

        if ((stack_en) && (!SYS_AT_BMP_IS_SET(p_serdes_cfg->flag, CTC_DATAPATH_SERDES_FLAG_LPORT_VALID)))
        {
            high_prio_port++;
            if (SYS_SPECIAL_RSV_PORT_START == high_prio_port)
            {
                high_prio_port += SYS_SPECIAL_RSV_PORT_NUM;
            }
        }
        else
        {
            inferior_port++;
            if (SYS_SPECIAL_RSV_PORT_START == inferior_port)
            {
                inferior_port += SYS_SPECIAL_RSV_PORT_NUM;
            }
        }
    }

    SYS_INTERNAL_PORT_START = (inferior_port > high_prio_port) ? inferior_port : high_prio_port;

    return CTC_E_NONE;
}

int32
_sys_at_datapath_get_port_chan_by_serdes(uint8 lchip, uint16 logic_serdes, uint16* p_chan, uint16* p_dport)
{
    uint8  core_id     = 0;
    uint16 chan_idx    = 0;
    uint8  occupy_flag = 0;
    uint16 lsd         = 0;
    uint16 dport       = 0;

    for (core_id = 0; core_id < SYS_AT_CORE_NUM; core_id++)
    {
        for(chan_idx = 0; chan_idx < AT_MAX_NW_CHAN_PER_CORE; chan_idx++)
        {
            SYS_CONDITION_CONTINUE(CTC_E_NONE != sys_usw_dmps_db_get_chan2lsd(lchip, core_id, chan_idx, &occupy_flag, &lsd, &dport));
            SYS_CONDITION_CONTINUE(SYS_DP_CHAN_LPORT_OCCUPY_RSV == occupy_flag);
            if(logic_serdes == lsd)
            {
                SYS_USW_VALID_PTR_WRITE(p_chan, SYS_AT_GET_CHAN_ID_BY_CORE(core_id, chan_idx));
                SYS_USW_VALID_PTR_WRITE(p_dport, dport);
                return CTC_E_NONE;
            }
        }
    }
    SYS_USW_VALID_PTR_WRITE(p_chan,  DMPS_INVALID_VALUE_U16);
    SYS_USW_VALID_PTR_WRITE(p_dport, DMPS_INVALID_VALUE_U16);

    return CTC_E_INVALID_CONFIG;
}

int32
_sys_at_datapath_get_serdes_chan_by_lport(uint8 lchip, uint16 dport, uint16* p_chan, uint16* p_logic_serdes)
{
    uint8  core_id     = 0;
    uint16 chan_idx    = 0;
    uint8  occupy_flag = 0;
    uint16 lsd         = 0;
    uint16 dport_tmp   = 0;

    for (core_id = 0; core_id < SYS_AT_CORE_NUM; core_id++)
    {
        for(chan_idx = 0; chan_idx < AT_CHAN_NUM_PER_CORE; chan_idx++)
        {
            SYS_CONDITION_CONTINUE(CTC_E_NONE != sys_usw_dmps_db_get_chan2lsd(lchip, core_id, chan_idx, &occupy_flag, &lsd, &dport_tmp));
            SYS_CONDITION_CONTINUE(SYS_DP_CHAN_LPORT_OCCUPY_RSV == occupy_flag);
            if(dport == dport_tmp)
            {
                SYS_USW_VALID_PTR_WRITE(p_chan, SYS_AT_GET_CHAN_ID_BY_CORE(core_id, chan_idx));
                SYS_USW_VALID_PTR_WRITE(p_logic_serdes, lsd);
                return CTC_E_NONE;
            }
        }
    }

    SYS_USW_VALID_PTR_WRITE(p_chan,  DMPS_INVALID_VALUE_U16);
    SYS_USW_VALID_PTR_WRITE(p_logic_serdes, DMPS_INVALID_VALUE_U16);

    return CTC_E_INVALID_CONFIG;
}

int32
sys_at_datapath_show_xpipe(uint8 lchip)
{
    uint8  port_type = 0;
    uint8  xpipe_en  = 0;
    uint8  core_id   = 0;
    uint8  pp_id     = 0;
    uint8  dp_id     = 0;
    uint8  txqm_id   = 0;
    uint8  chan_num  = 0;
    uint8  idx       = 0;
    uint16 lport     = 0;
    uint16 dport     = 0;
    uint16 chan_list[DMPS_MAX_NUM_PER_MODULE]  = {0};
    uint16 mac_client[DMPS_MAX_NUM_PER_MODULE] = {0};
    uint16 sub_chan[DMPS_MAX_NUM_PER_MODULE]   = {0};
    sys_dmps_db_upt_info_t port_info           = {0};

    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "------------------------------------------------------------------------------------------------------------------------------------------------------------------------------\n");
    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " %-7s%-6s%-4s%-4s%-6s%-10s%-6s%-7s%-7s%-7s%-7s%-7s%-7s%-7s%-7s%-7s%-6s%-7s%-7s%-7s%-7s%-7s%-7s%-7s%-7s%-7s\n",
        "LPORT", "CORE", "PP", "DP", "TXQM", "XPIPE-EN",
        "| Tx:", "CHAN0", "SUB0", "MAC0", "CHAN1", "SUB1", "MAC1", "CHAN2", "SUB2", "MAC2",
        "| Rx:", "CHAN0", "SUB0", "MAC0", "CHAN1", "SUB1", "MAC1", "CHAN2", "SUB2", "MAC2");
    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "------------------------------------------------------------------------------------------------------------------------------------------------------------------------------\n");
    for(lport = 0; lport < SYS_USW_MAX_PORT_NUM_PER_CHIP; lport++)
    {
        sal_memset(chan_list,  0xff, DMPS_MAX_NUM_PER_MODULE * sizeof(uint16));
        sal_memset(mac_client, 0xff, DMPS_MAX_NUM_PER_MODULE * sizeof(uint16));
        sal_memset(sub_chan,   0xff, DMPS_MAX_NUM_PER_MODULE * sizeof(uint16));
        chan_num = 0;

        (void) sys_usw_dmps_db_lport_2_dport(lchip, lport ,&dport);
        SYS_CONDITION_CONTINUE(!sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport));

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_XPIPE_EN);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_PP_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_DP_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_TXQM_ID);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,          port_type);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_XPIPE_EN,      xpipe_en);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,       core_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_PP_ID,         pp_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_DP_ID,         dp_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_TXQM_ID,       txqm_id);

        SYS_CONDITION_CONTINUE((SYS_DMPS_NETWORK_PORT != port_type) || (0 == xpipe_en));

        CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, DMPS_DB_TYPE_CHAN, &chan_num, chan_list));
        SYS_CONDITION_CONTINUE((0 == chan_num) || (chan_num > DMPS_MAX_NUM_PER_MODULE));
        for (idx = 0; idx < chan_num; idx++)
        {
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_list[idx]);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SUB_CHAN_ID);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID,   sub_chan[idx]);
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID, mac_client[idx]);
        }

        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " %-7u%-6u%-4u%-4u%-6u%-10u%-6s%-7u%-7u%-7u%-7u%-7u%-7u%-7u%-7u%-7u",
            lport, core_id, pp_id, dp_id, txqm_id, xpipe_en, "", chan_list[0], sub_chan[0], mac_client[0],
            chan_list[1], sub_chan[1], mac_client[1], chan_list[2], sub_chan[2], mac_client[2]);

        sal_memset(chan_list,  0xff, DMPS_MAX_NUM_PER_MODULE * sizeof(uint16));
        sal_memset(mac_client, 0xff, DMPS_MAX_NUM_PER_MODULE * sizeof(uint16));
        sal_memset(sub_chan,   0xff, DMPS_MAX_NUM_PER_MODULE * sizeof(uint16));
        chan_num = 0;

        CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, DMPS_DB_TYPE_CHAN_RX, &chan_num, chan_list));
        SYS_CONDITION_CONTINUE((0 == chan_num) || (chan_num > DMPS_MAX_NUM_PER_MODULE));
        for (idx = 0; idx < chan_num; idx++)
        {
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_RX_ID, chan_list[idx]);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_RX_SUB_CHAN_ID);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_RX_MAC_CLIENT_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_SUB_CHAN_ID,   sub_chan[idx]);
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_MAC_CLIENT_ID, mac_client[idx]);
        }

        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-6s%-7u%-7u%-7u%-7u%-7u%-7u%-7u%-7u%-7u\n",
            "", chan_list[0], sub_chan[0], mac_client[0],
            chan_list[1], sub_chan[1], mac_client[1], chan_list[2], sub_chan[2], mac_client[2]);
    }

    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "------------------------------------------------------------------------------------------------------------------------------------------------------------------------------\n");
    return CTC_E_NONE;
}

int32
_sys_at_datapath_init_mapping(uint8 lchip, ctc_datapath_global_cfg_t* p_cfg)
{
    uint8  chip_type          = 0;
    uint8  core_num           = 0;
    uint8  pcs_l              = 0;
    uint8  mac_group_id       = 0;
    uint8  mac_idx            = 0;
    uint8  pcs_idx            = 0;
    uint8  if_mode            = CTC_CHIP_MAX_SERDES_MODE;
    uint8  logic_lane         = 0;
    uint8  lane_num           = 0;
    uint8  lane_idx           = 0;
    uint8  core_id            = 0;
    uint8  fec_type           = SYS_DMPS_FEC_TYPE_NONE;
    uint8  if_type            = 0;
    uint8  speed_mode         = 0;
    uint8  physic_lane_id     = 0;
    uint8  rsv_port_flag      = TRUE;
    uint16 mac_id             = 0;
    uint16 pcs_id             = 0;
    uint16 dport              = 0;
    uint16 dport_prv          = DMPS_INVALID_VALUE_U16;
    uint16 chan_prv           = DMPS_INVALID_VALUE_U16;
    uint16 chan_id            = 0;
    uint16 logic_serdes_sc    = 0; /*logic serdes single-core (0~159)*/
    uint16 logic_serdes_dc    = 0; /*logic serdes dual-core (0~319)*/
    uint16 physic_serdes      = 0;
    uint32 support_speed      = 0;
    uint32 serdes_speed       = 0;
    uint32 speed_value        = 0;
    sys_dmps_serdes_speed_t             speed = 0;
    sys_dmps_db_upt_info_t port_info          = {0};
    sys_dmps_db_upt_info_t port_info_p        = {0};
    const sys_at_dmps_id_dictionary_t* p_dictionary = NULL;
    ctc_datapath_serdes_prop_t*  p_serdes_cfg = NULL;

    chip_type = SYS_AT_GET_CHIP_TYPE(lchip);
    core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

    /*determine which subtype dictionary to use*/
    SYS_AT_GET_DIC_BY_CHIP_TYPE(chip_type, p_dictionary);
    if (NULL == p_dictionary)
    {
        return CTC_E_INVALID_CONFIG;
    }

    /* NetWork database init */
    for(core_id = 0; core_id < core_num; core_id++)
    {
        for (logic_serdes_sc = 0; logic_serdes_sc < SYS_AT_NW_SERDES_NUM_PER_CORE; logic_serdes_sc++)
        {
            /*skip invalid lanes*/
            SYS_CONDITION_CONTINUE(SYS_DMPS_INVALID_U8 == p_dictionary[logic_serdes_sc].pp_id);
            logic_serdes_dc = SYS_AT_GET_LOGIC_SERDES_DC(core_id, logic_serdes_sc);
            p_serdes_cfg    = &(p_cfg->serdes[logic_serdes_dc]);
            SYS_CONDITION_CONTINUE(NULL == p_serdes_cfg);

            /* get chan and lport by logical serdes id */
            (void) _sys_at_datapath_get_port_chan_by_serdes(lchip, logic_serdes_dc, &chan_id, &dport);
            if ((chan_id >= DMPS_MAX_CHAN_NUM) || (dport >= DMPS_MAX_PORT_NUM))
            {
                rsv_port_flag = FALSE;
            }
            else
            {
                rsv_port_flag = TRUE;
            }

            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));

            mac_group_id    = SYS_AT_GET_MAC_GROUP_BY_LSD_SC(logic_serdes_sc);
            SYS_CONDITION_CONTINUE(!SYS_AT_MAC_GROUP_IS_VAILD(lchip, core_id, mac_group_id));

            /*info collection*/
            if_mode       = p_serdes_cfg->mode;
            if_mode       = (SYS_AT_IS_SUPPORT_NW(if_mode)) ? if_mode : CTC_CHIP_SERDES_NONE_MODE;
            SYS_AT_GET_LANE_NUM_BY_MODE(if_mode, lane_num);
            logic_lane    = SYS_AT_GET_LANE_IN_GROUP(logic_serdes_dc);
            physic_serdes = p_serdes_cfg->physical_serdes_id;
            if ((SYS_DMPS_INVALID_U16 == physic_serdes) ||
                ((SYS_SERDES_DYN_FORBID_ALL == p_serdes_cfg->is_dynamic) && (0 == lane_num)))
            {
                continue;
            }

#ifdef EMULATION_ENV
#ifndef PCS_ONLY
            if (!((SYS_AT_IS_1PP(chip_type)) && ((16 == mac_group_id) || (17 == mac_group_id))))
            {
                /* 1pp: CtcMac 16&17 support lane swap, but CtcMac 18&19 cannot support */
                physic_serdes = logic_serdes_dc;
            }
#endif
#endif

            if(0 == lane_num)
            {
                pcs_l  = SYS_AT_USELESS_ID8;
                mac_id = logic_serdes_dc;
                pcs_id = mac_id;

                /* MAC DB */
                DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_MAC_EN,       FALSE);
                DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_MAC_SPEED,    0);
                DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
                DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      SYS_AT_GET_MAC_IDX_BY_ID(mac_id));

                /* PCS DB */
                DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,      SYS_AT_GET_MAC_IDX_BY_ID(mac_id));

                if (rsv_port_flag)
                {
                    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info_p));
                    /* PORT DB */
                    DMPS_DB_SET_MAP_INFO(port_info_p, DMPS_DB_DPORT,                   dport); 
                    DMPS_DB_SET_PROPERTY_INFO(port_info_p, DMPS_DB_PORT_TYPE,          SYS_DMPS_RSV_PORT);
                    DMPS_DB_SET_PROPERTY_INFO(port_info_p, DMPS_DB_PORT_IF_MODE,       CTC_CHIP_SERDES_NONE_MODE);
                    DMPS_DB_SET_PROPERTY_INFO(port_info_p, DMPS_DB_PORT_IS_AN_FIRST,   0);
                    DMPS_DB_SET_PROPERTY_INFO(port_info_p, DMPS_DB_PORT_LINK_FSM,      PMA_RX_NONREADY);
                    DMPS_DB_SET_PROPERTY_INFO(port_info_p, DMPS_DB_PORT_LINK_MODE,     g_port_link_mode);

                    CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &port_info_p));
                }

                dport   = SYS_DMPS_INVALID_U16;
                chan_id = SYS_DMPS_INVALID_U16;
            }
            else
            {
                pcs_l    = SYS_AT_GET_MACID_BY_LOGIC_SERDES(logic_serdes_dc) % lane_num;
                mac_id   = SYS_AT_GET_MACID_BY_LOGIC_SERDES(logic_serdes_dc) / lane_num * lane_num;
                mac_idx  = SYS_AT_GET_MAC_IDX_BY_ID(mac_id);
                pcs_id   = mac_id;
                pcs_idx  = mac_idx;
                fec_type = SYS_DMPS_IS_PAM4_MODE(if_mode) ? SYS_DMPS_FEC_TYPE_RS544 : SYS_DMPS_FEC_TYPE_NONE;

                if(0 == pcs_l)
                {
                    /*check the conformity of multi-lane mode configuration */
                    if (lane_num > 1)
                    {
                        for (lane_idx = 1; lane_idx < lane_num; lane_idx++)
                        {
                            if (p_cfg->serdes[logic_serdes_dc+lane_idx].mode != if_mode)
                            {
                                SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Multi-lane[%d-%d] mode mismatch.\n", logic_serdes_dc, logic_serdes_dc+lane_idx);
                                return CTC_E_INVALID_CONFIG;
                            }
                        }
                    }

                    /* MAC DB */
                    DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_MAC_EN,       FALSE);
                    DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_MAC_SPEED,    0);
                    DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID, mac_group_id);
                    DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,      mac_idx);

                    /* PCS DB */
                    DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,      pcs_idx);

                    if (rsv_port_flag)
                    {
                        SYS_AT_GET_PORT_IFTYPE(if_mode, if_type);
                        SYS_DMPS_GET_PORT_SPEED(if_mode, speed_mode);
                        SYS_USW_GET_SPEED_VALUE(speed_mode, fec_type, CTC_CHIP_SERDES_OCS_MODE_NONE, speed_value);

                        /* PORT DB */
                        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,          SYS_DMPS_NETWORK_PORT);
                        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,       if_mode);
                        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_FEC_TYPE,      fec_type);
                        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_TYPE,       if_type);
                        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IS_AN_FIRST,   0);
                        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_LINK_FSM,      PMA_RX_NONREADY);
                        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_LINK_MODE,     g_port_link_mode);

                        /* CHAN DB */
                        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE,    speed_mode);
                        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_SPEED_MODE, speed_mode);
                        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_VALUE,   speed_value);
                        DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_SPEED_VALUE,speed_value);
                    }
                }
                else
                {
                    /*check the conformity of multi-lane mode configuration */
                    if ((lane_num > 1) && (p_cfg->serdes[logic_serdes_dc-pcs_l].mode != if_mode))
                    {
                        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Multi-lane[%d-%d] mode mismatch.\n", logic_serdes_dc-pcs_l, logic_serdes_dc);
                        return CTC_E_INVALID_CONFIG;
                    }

                    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info_p));
                    DMPS_DB_SET_MAP_INFO(port_info_p, DMPS_DB_MAC_ID, mac_id + pcs_l);
                    DMPS_DB_SET_MAP_INFO(port_info_p, DMPS_DB_PCS_ID, pcs_id + pcs_l);
                    DMPS_DB_SET_PROPERTY_INFO(port_info_p, DMPS_DB_MAC_GROUP_ID, mac_group_id);
                    DMPS_DB_SET_PROPERTY_INFO(port_info_p, DMPS_DB_MAC_IDX,      mac_idx + pcs_l);
                    DMPS_DB_SET_PROPERTY_INFO(port_info_p, DMPS_DB_PCS_IDX,      pcs_idx + pcs_l);

                    if (rsv_port_flag)
                    {
                        /* PORT DB */
                        DMPS_DB_SET_MAP_INFO(port_info_p, DMPS_DB_DPORT,   dport); 
                        DMPS_DB_SET_PROPERTY_INFO(port_info_p, DMPS_DB_PORT_TYPE,          SYS_DMPS_RSV_PORT);
                        DMPS_DB_SET_PROPERTY_INFO(port_info_p, DMPS_DB_PORT_IS_AN_FIRST,   0);
                        DMPS_DB_SET_PROPERTY_INFO(port_info_p, DMPS_DB_PORT_LINK_FSM,      PMA_RX_NONREADY);
                        DMPS_DB_SET_PROPERTY_INFO(port_info_p, DMPS_DB_PORT_LINK_MODE,     g_port_link_mode);
                    }

                    CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &port_info_p)); 

                    dport   = dport_prv;
                    chan_id = chan_prv;
                }
            }

            /* LOGIC SERDES DB */
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_IS_DYN,   p_serdes_cfg->is_dynamic);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_LSD_LANE_ID,  logic_lane);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_LSD_PCSL_IDX, ((0 == lane_num) ? 0 : logic_serdes_dc % lane_num));
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_LSD_HSS_ID,   SYS_AT_MAP_SERDES_TO_HSS_IDX(logic_serdes_dc));

            /* PHYSIC SERDES DB */
            physic_lane_id = SYS_AT_GET_LANE_IN_GROUP(physic_serdes);
            support_speed  = _sys_at_datapath_get_serdes_support_speed_bmp(lchip, chip_type, logic_serdes_dc);
            speed          = sys_usw_dmps_get_speed_from_serdes_info(if_mode, fec_type, CTC_CHIP_SERDES_OCS_MODE_NONE);
            if (!((1 << speed) & support_speed))
            {
                SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " %% Serdes %d cannot support speed %d!\n", physic_serdes, speed);
                return CTC_E_INVALID_CONFIG;
            }
            SYS_USW_SERDES_SPEED_2_VALUE(speed, serdes_speed);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_PLL_SEL,       0);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_RATE_DIV,      0);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_BIT_WIDTH,     0);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_RX_POLARITY,   p_serdes_cfg->rx_polarity);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_TX_POLARITY,   p_serdes_cfg->tx_polarity);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_OCS,           CTC_CHIP_SERDES_OCS_MODE_NONE);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_LANE_ID,       physic_lane_id);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_SUPPORT_SPEED, support_speed);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_SPEED,         serdes_speed);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_RX_POLARITY,   
                (0 == p_serdes_cfg->rx_polarity) ? DMPS_POLARITY_NORM : DMPS_POLARITY_INV);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_TX_POLARITY,   
                (0 == p_serdes_cfg->tx_polarity) ? DMPS_POLARITY_NORM : DMPS_POLARITY_INV);

            /*build map_node_list*/
            DMPS_DB_SET_MAP_UPDATE(port_info);
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,         dport);
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID,       chan_id);
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_RX_ID,    chan_id);
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_MAC_ID,        mac_id);
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_PCS_ID,        pcs_id);
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES,  logic_serdes_dc);
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_PHYSIC_SERDES, physic_serdes);

            CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &port_info));

            /* check mag group bw */
            CTC_ERROR_RETURN(_sys_at_mac_group_check_bw(lchip, core_id, mac_group_id, NULL));

            /*ready for duplication check*/
            dport_prv  = dport;
            chan_prv   = chan_id;
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_init_cpumac_mapping(uint8 lchip, ctc_datapath_global_cfg_t* p_cfg)
{
    uint8  chip_type          = 0;
    uint8  core_num           = 0;
    uint8  core_id            = 0;
    uint8  mode               = 0;
    uint8  pp_id              = 0;
    uint8  dp_id              = 0;
    uint8  port_type          = 0;
    uint8  speed_mode         = 0;
    uint8  if_type            = 0;
    uint8  idx                = 0;
    uint8  bpe_full_mode      = 0;
    uint16 dport              = SYS_INTERNAL_PORT_START;
    uint16 lport              = SYS_INTERNAL_PORT_START;
    uint16 mac_id             = 0;
    uint16 pcs_id             = 0;
    uint16 chan_id            = 0;
    uint16 chan_idx           = 0;
    uint16 psd                = 0;
    uint16 lsd                = 0;
    uint32 support_speed      = 0;
    uint32 serdes_speed       = 0;
    uint32 speed_value        = 0;
    sys_dmps_db_upt_info_t    port_info = {0};
    sys_dmps_serdes_speed_t   speed     = 0;
    sys_dmps_db_cpumac_map_t  p_map     = {0};

    if (CTC_WB_ENABLE(lchip) && CTC_WB_STATUS(lchip) == CTC_WB_STATUS_RELOADING)
    {
        return CTC_E_NONE;
    }

    chip_type = SYS_AT_GET_CHIP_TYPE(lchip);
    core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_bpe_full_mode(lchip, &bpe_full_mode));

    for (core_id = 0; core_id < core_num; core_id++)
    {
        for (idx = 0; idx < AT_CPUMAC_PER_CORE; idx++)
        {
            p_map.lport      = DMPS_INVALID_VALUE_U16;
            p_map.is_network = FALSE;

            lsd = DMPS_MAX_SERDES_NUM_PER_CORE * DMPS_MAX_CORE_NUM + core_id * AT_CPUMAC_PER_CORE + idx;
            mode = p_cfg->serdes[lsd].mode;
            mode = (SYS_AT_IS_SUPPORT_CPUMAC(mode)) ? mode : CTC_CHIP_SERDES_NONE_MODE;
            if (!SYS_AT_IS_MODE_VALID_CPUMAC(mode))
            {
                /* cpumac donnot  support PAM4  mode */
                return CTC_E_INVALID_CONFIG;
            }

            if ((SYS_SERDES_DYN_FORBID_ALL == p_cfg->serdes[lsd].is_dynamic) && (CTC_CHIP_SERDES_NONE_MODE == mode))
            {
                continue;
            }

            chan_idx = AT_NW_CHAN_NUM_PER_CORE + idx;
            pp_id    = idx;    /* pp0/pp1 */
            dp_id    = 1;      /* dp1 */
            if (((0 == core_id) && (p_cfg->cpumac_dp0_network_en))
                || ((1 == core_id) && (p_cfg->cpumac_dp1_network_en)))
            {
                port_type = SYS_DMPS_CPUMAC_NETWORK_PORT;
                chan_id   = SYS_AT_CHAN_CPUMAC_NETWORK_START + core_id * AT_CPUMAC_PER_CORE + idx;
                p_map.is_network = TRUE;
            }
            else
            {
                port_type = SYS_DMPS_CPU_MAC_PORT;
                chan_id   = SYS_AT_CHAN_CPUMAC_START + core_id * AT_CPUMAC_PER_CORE + idx;
            }

            port_type = (CTC_CHIP_SERDES_NONE_MODE == mode) ? SYS_DMPS_RSV_PORT : port_type;

            if (!bpe_full_mode)
            {
                /*init lport-dport map*/
                CTC_ERROR_RETURN(sys_usw_dmps_db_set_ext_lport_map(lchip, lport, dport));
            }

            CTC_ERROR_RETURN(sys_usw_dmps_db_set_chan2lsd(lchip, core_id, chan_idx, SYS_DP_CHAN_LPORT_OCCUPY_IN_USE, lsd, dport));

            /* opf: Assign channel and port */
            CTC_ERROR_RETURN(sys_usw_dmps_db_assign_chan(lchip, chan_id));
            CTC_ERROR_RETURN(sys_usw_dmps_db_assign_port(lchip, lport));

            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));

            SYS_DMPS_GET_PORT_SPEED(mode, speed_mode);
            SYS_USW_GET_SPEED_VALUE(speed_mode, SYS_DMPS_FEC_TYPE_NONE, CTC_CHIP_SERDES_OCS_MODE_NONE, speed_value);

            /* Config port db */
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,                   dport);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,          port_type);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IS_RSV,        TRUE);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IDX,           idx);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_MODE,       mode);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_FEC_TYPE,      SYS_DMPS_FEC_TYPE_NONE);
            SYS_AT_GET_PORT_IFTYPE(mode, if_type);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_TYPE,       if_type);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_LINK_FSM,      PMA_RX_NONREADY);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_LINK_MODE,     g_port_link_mode);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IS_AN_FIRST,   0);

            /* Config chan db */
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID,                 chan_id);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,       core_id);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_PP_ID,         pp_id);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_DP_ID,         dp_id);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_TXQM_ID,       SYS_AT_USELESS_ID8);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID, SYS_AT_MISC_MAC_CLIENT_IN_DP);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID,   SYS_AT_MISC_CHAN_ID_IN_DP);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_PRIO,          FALSE);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_IS_RSV,        TRUE);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE,    speed_mode);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_VALUE,   speed_value);

            /* Config chan rx db */
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_RX_ID,                 chan_id);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_CORE_ID,       core_id);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_PP_ID,         pp_id);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_DP_ID,         dp_id);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_TXQM_ID,       SYS_AT_USELESS_ID8);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_MAC_CLIENT_ID, SYS_AT_MISC_MAC_CLIENT_IN_DP);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_SUB_CHAN_ID,   SYS_AT_MISC_CHAN_ID_IN_DP);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_PRIO,          FALSE);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_IS_RSV,        TRUE);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_SPEED_MODE,    speed_mode);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_RX_SPEED_VALUE,   speed_value);

            CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &port_info));

            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));

            /* Config mac db */
            mac_id = lsd;
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_MAC_GROUP_ID,       SYS_AT_USELESS_ID8);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_MAC_IDX,            idx);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_MAC_EN,             FALSE);

            /* Config pcs db */
            pcs_id = mac_id;
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX,            idx);

            /* Config logical serdes db */
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_LSD_LANE_ID,       idx);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_LSD_PCSL_IDX,      0);

            /* Config physical serdes db */
            psd                = p_cfg->serdes[lsd].physical_serdes_id;
            support_speed      = _sys_at_datapath_get_serdes_support_speed_bmp(lchip, chip_type, lsd);
            speed              = sys_usw_dmps_get_speed_from_serdes_info(mode, SYS_DMPS_FEC_TYPE_NONE, CTC_CHIP_SERDES_OCS_MODE_NONE);
            if (!((1 << speed) & support_speed))
            {
                SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " %% Serdes %d cannot support speed %d !\n", psd, speed);
                return CTC_E_INVALID_CONFIG;
            }
            SYS_USW_SERDES_SPEED_2_VALUE(speed, serdes_speed);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_SPEED,         serdes_speed);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_SUPPORT_SPEED, support_speed);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_LANE_ID,       psd % AT_SERDES_NUM_PER_MCMAC);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_RX_POLARITY,   p_cfg->serdes[lsd].rx_polarity);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_TX_POLARITY,   p_cfg->serdes[lsd].tx_polarity);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_IS_DYN,        p_cfg->serdes[lsd].is_dynamic);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_BIT_WIDTH,     0);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_PLL_SEL,       0);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_RATE_DIV,      0);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_RX_POLARITY,   
                (0 == p_cfg->serdes[lsd].rx_polarity) ? DMPS_POLARITY_NORM : DMPS_POLARITY_INV);
            DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PSD_TX_POLARITY,   
                (0 == p_cfg->serdes[lsd].tx_polarity) ? DMPS_POLARITY_NORM : DMPS_POLARITY_INV);

            DMPS_DB_SET_MAP_UPDATE(port_info);
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES,  lsd);
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_PHYSIC_SERDES, psd);

            if (CTC_CHIP_SERDES_NONE_MODE == mode)
            {
                DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,         SYS_DMPS_INVALID_U16);
                DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID,       SYS_DMPS_INVALID_U16);
                DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_RX_ID,    SYS_DMPS_INVALID_U16);
            }
            else
            {
                DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,         dport);
                DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID,       chan_id);
                DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_RX_ID,    chan_id);
            }
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_MAC_ID,        mac_id);
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_PCS_ID,        pcs_id);

            CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &port_info));

            p_map.lport = dport;
            CTC_ERROR_RETURN(sys_usw_dmps_db_set_cpumac_map(lchip, core_id * AT_CPUMAC_PER_CORE + idx, &p_map));

            dport++;
            if (SYS_SPECIAL_RSV_PORT_START == dport)
            {
                dport += SYS_SPECIAL_RSV_PORT_NUM;
            }
            lport = dport;
        }
    }

    SYS_INTERNAL_PORT_START = lport;

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_bs_mode(uint8 lchip, sys_dmps_db_chan_info_t* chan_info)
{
    uint8  core          = 0;
    uint16 speed         = 0;
    uint16 sub_chan_id   = 0;
    uint32 entry         = 0;
    uint32 value         = 0;
    uint32 cmd           = 0;
    uint32 index         = 0;
    BsUcMsgSndMode_m      bs_mode;

    CTC_PTR_VALID_CHECK(chan_info);
    sub_chan_id   = chan_info->sub_chan_id;

    SYS_DATAPATH_SYS_MODE_TO_SPEED(chan_info->speed_mode, speed);
    SYS_AT_SPEED_TO_BS_MODE(speed, value);

    /* local core */
    core  = chan_info->core_id;
    entry = chan_info->pp_id * SYS_AT_CHAN_NUM_PER_PP + chan_info->dp_id * SYS_AT_CHAN_NUM_PER_DP + sub_chan_id;

    index = DRV_INS(0, entry);
    cmd   = DRV_IOR(BsUcMsgSndMode_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &bs_mode));

    DRV_IOW_ENTRY_NZ(core, 0xff, 0xff, lchip, BsUcMsgSndMode_t, 0, entry, BsUcMsgSndMode_mode_f, &value, &bs_mode);

    cmd = DRV_IOW(BsUcMsgSndMode_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &bs_mode));

    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        /* remote core */
        core  = (0 == chan_info->core_id) ? 1 : 0;
        entry = AT_CHAN_NUM_PER_CORE + chan_info->pp_id * SYS_AT_CHAN_NUM_PER_PP +
                    chan_info->dp_id * SYS_AT_CHAN_NUM_PER_DP + sub_chan_id;

        index = DRV_INS(0, entry);
        cmd   = DRV_IOR(BsUcMsgSndMode_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &bs_mode));

        DRV_IOW_ENTRY_NZ(core, 0xff, 0xff, lchip, BsUcMsgSndMode_t, 0, entry, BsUcMsgSndMode_mode_f, &value, &bs_mode);

        cmd = DRV_IOW(BsUcMsgSndMode_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &bs_mode));
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_br_mode(uint8 lchip, sys_dmps_db_chan_info_t* chan_info)
{
    uint8  core          = 0;
    uint16 speed         = 0;
    uint16 sub_chan_id   = 0;
    uint32 value         = 0;
    uint32 cmd           = 0;
    uint32 index         = 0;
    PreBrChanBufPtrMode_m pre_br_mode;

    CTC_PTR_VALID_CHECK(chan_info);
    sub_chan_id   = chan_info->sub_chan_id;

    SYS_DATAPATH_SYS_MODE_TO_SPEED(chan_info->speed_mode, speed);
    SYS_AT_SPEED_TO_BS_MODE(speed, value);

    /* local core */
    core  = chan_info->core_id;

    index = DRV_INS(0, sub_chan_id);
    cmd   = DRV_IOR(PreBrChanBufPtrMode_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, chan_info->pp_id, chan_info->dp_id, cmd, &pre_br_mode));

    DRV_IOW_ENTRY_NZ(core, chan_info->pp_id, chan_info->dp_id, lchip, PreBrChanBufPtrMode_t, 0, sub_chan_id,
        PreBrChanBufPtrMode_sopPtrCnt_f, &value, &pre_br_mode);

    cmd = DRV_IOW(PreBrChanBufPtrMode_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, chan_info->pp_id, chan_info->dp_id, cmd, &pre_br_mode));

    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        /* remote core */
        core  = (0 == chan_info->core_id) ? 1 : 0;
        index = DRV_INS(1, sub_chan_id);
        cmd   = DRV_IOR(PreBrChanBufPtrMode_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, chan_info->pp_id, chan_info->dp_id, cmd, &pre_br_mode));

        DRV_IOW_ENTRY_NZ(core, chan_info->pp_id, chan_info->dp_id, lchip, PreBrChanBufPtrMode_t, 1, sub_chan_id,
            PreBrChanBufPtrMode_sopPtrCnt_f, &value, &pre_br_mode);

        cmd = DRV_IOW(PreBrChanBufPtrMode_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, chan_info->pp_id, chan_info->dp_id, cmd, &pre_br_mode));
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_extra_cfg(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint32 cmd           = 0;
    uint32 val_32        = 0;
    uint32 index         = 0;
    uint32 dp_chan_id    = 0;
    DsChannelizeMode_m   mode;
    
    /*config max len*/
    for(dp_chan_id = 0; dp_chan_id < SYS_AT_CHAN_NUM_PER_DP; dp_chan_id++)
    {
        index = DRV_INS(0, dp_chan_id);
        cmd   = DRV_IOR(DsChannelizeMode_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &mode));

        val_32 = 9600;
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, DsChannelizeMode_t, 0, dp_chan_id, DsChannelizeMode_portMaxLen_f, &val_32, &mode);
        val_32 = 0;
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, DsChannelizeMode_t, 0, dp_chan_id, DsChannelizeMode_portMinLen_f, &val_32, &mode);

        cmd = DRV_IOW(DsChannelizeMode_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &mode));
    }

    dp_chan_id = SYS_AT_CHAN_NUM_PER_DP;
    index = DRV_INS(0, dp_chan_id);
    cmd   = DRV_IOR(DsChannelizeMode_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &mode));

    val_32 = 0x3fff;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, DsChannelizeMode_t, 0, dp_chan_id, DsChannelizeMode_portMaxLen_f, &val_32, &mode);
    val_32 = 0;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, DsChannelizeMode_t, 0, dp_chan_id, DsChannelizeMode_portMinLen_f, &val_32, &mode);

    cmd = DRV_IOW(DsChannelizeMode_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &mode));

    return CTC_E_NONE;
}

/*collecting mac id related speed and creating a temp database cal_info[], to improve calendar calculating efficiency*/
int32
_sys_at_calendar_speed_info_collect(uint8 lchip, sys_at_cal_info_collect_t cal_info[],
                                    uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 dp_txqm_id, uint8 cal_type)
{
    uint8  is_valid           = FALSE;
    uint8  is_cpumac_cal      = FALSE;
    uint8  is_rsv             = 0;
    uint8  ock                = CTC_CHIP_SERDES_OCS_MODE_NONE;
    uint8  level              = AT_MAX_LEVEL;
    uint8  index_type         = 0; /* 0: index by chan; 1: index by mac_client */
    uint8  chan_idx           = 0;
    uint8  port_type          = 0;
    uint8  speed_mode         = 0;
    uint8  if_type            = 0;
    uint8  dp                 = 0;
    uint8  dir_bmp            = 0;
    uint8  p_chan_num         = 0;
    uint16 dport              = 0;
    uint16 index              = 0;
    uint16 chan_id            = 0;
    uint16 sub_chan_id        = 0;
    uint16 mac_client_id      = 0;
    uint32 speed              = 0;
    uint16 p_chan_id[SYS_AT_CHAN_NUM_PER_PP] = {0};
    uint16 chan_list[SYS_AT_CHAN_NUM_PER_PP] = {0};
    sys_dmps_db_upt_info_t port_info         = {0};

    sal_memset(cal_info, 0, sizeof(sys_at_cal_info_collect_t) * SYS_AT_CHAN_NUM_PER_PP);

    /*judge calendar type to get proper options, which determine how to collect speed info*/
    switch(cal_type)
    {
        case SYS_AT_NETRX_CAL:
            is_cpumac_cal = FALSE;
            index_type    = 1;
            level         = AT_DP_LEVEL;
            dir_bmp       = CHAN_DIR_RX;
            break;
        case SYS_AT_EPE_CAL:
            is_cpumac_cal = TRUE;
            index_type    = 1;
            level         = AT_DP_LEVEL;
            dir_bmp       = CHAN_DIR_TX;
            break;
        case SYS_AT_BR_CAL:
            is_cpumac_cal = TRUE;
            index_type    = 0;
            level         = AT_DP_LEVEL;
            dir_bmp       = CHAN_DIR_TX;
            break;
        case SYS_AT_NETTX_CAL:
            is_cpumac_cal = FALSE;
            index_type    = 1;
            level         = AT_TXQM_LEVEL;
            dir_bmp       = CHAN_DIR_TX;
            break;
        case SYS_AT_QMGR_CAL:
            is_cpumac_cal = TRUE;
            index_type    = 0;
            level         = AT_PP_LEVEL;
            dir_bmp       = CHAN_DIR_TX;
            break;
        default:
            return CTC_E_INVALID_PARAM;
    }

    /* network chan */
    for (chan_idx = 0; chan_idx < SYS_AT_NW_CHAN_NUM_PER_PP; chan_idx++)
    {
        chan_id = core_id * AT_NW_CHAN_NUM_PER_CORE + pp_id * SYS_AT_NW_CHAN_NUM_PER_PP + chan_idx;
        chan_list[chan_idx] = chan_id;
    }

    /* dp 0 chan 24 */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, 0, SYS_AT_MISC_CHAN_ID_IN_DP, &chan_id, dir_bmp));
    chan_list[SYS_AT_NW_CHAN_NUM_PER_PP] = chan_id;

    /* dp 0 chan 25 */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, 0, SYS_AT_LOOP_CHAN_ID_IN_DP, &chan_id, dir_bmp));
    chan_list[SYS_AT_NW_CHAN_NUM_PER_PP + 1] = chan_id;

    /* dp 1 chan 24 */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, 1, SYS_AT_MISC_CHAN_ID_IN_DP, &chan_id, dir_bmp));
    chan_list[SYS_AT_NW_CHAN_NUM_PER_PP + 2] = chan_id;

    /* dp 1 chan 25 */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, 1, SYS_AT_LOOP_CHAN_ID_IN_DP, &chan_id, dir_bmp));
    chan_list[SYS_AT_NW_CHAN_NUM_PER_PP + 3] = chan_id;

    for (chan_idx = 0; chan_idx < SYS_AT_CHAN_NUM_PER_PP; chan_idx++)
    {
        chan_id  = chan_list[chan_idx];
        is_valid = TRUE;
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, GET_CHAN_TYPE_BY_DIR(dir_bmp), chan_id));

        switch (level)
        {
            case AT_PP_LEVEL:
                if (!_sys_at_datapath_is_same_core_pp_dp_txqm(lchip, chan_id, core_id, pp_id, DMPS_INVALID_VALUE_U8, DMPS_INVALID_VALUE_U8, dir_bmp))
                {
                    is_valid = FALSE;
                }
                break;
            case AT_DP_LEVEL:
                if (!_sys_at_datapath_is_same_core_pp_dp_txqm(lchip, chan_id, core_id, pp_id, dp_id, DMPS_INVALID_VALUE_U8, dir_bmp))
                {
                    is_valid = FALSE;
                }
                break;
            case AT_TXQM_LEVEL:
                if (!_sys_at_datapath_is_same_core_pp_dp_txqm(lchip, chan_id, core_id, pp_id, dp_id, dp_txqm_id, dir_bmp))
                {
                    is_valid = FALSE;
                }
                break;
            default:
                break;
        }
        if (!is_valid)
        {
            continue;
        }

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, GET_CHAN_ID_BY_DIR(dir_bmp), chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_IF_TYPE);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_DP_ID_BY_DIR(dir_bmp));
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp));
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp));
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_SPEED_MODE_BY_DIR(dir_bmp));
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, GET_IS_RSV_BY_DIR(dir_bmp));
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_MAP_INFO(port_info, DMPS_DB_DPORT,                      dport);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,             port_type);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_IF_TYPE,          if_type);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_DP_ID_BY_DIR(dir_bmp),         dp);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp),   sub_chan_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp), mac_client_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_SPEED_MODE_BY_DIR(dir_bmp),    speed_mode);
        DMPS_DB_GET_PROPERTY_INFO(port_info, GET_IS_RSV_BY_DIR(dir_bmp),        is_rsv);

        if (sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport))
        {
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PSD_OCS);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PSD_OCS, ock);
        }

        /* nettx: only cfg the original mac_client channel */
        if (SYS_AT_NETTX_CAL == cal_type)
        {
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_PORT, dport, DMPS_DB_TYPE_CHAN, &p_chan_num, p_chan_id));
            if ((chan_id != p_chan_id[p_chan_num - 1]) || ((1 == p_chan_num) && (0 == is_rsv)))
            {
                continue;
            }
        }

        if ((SYS_DMPS_NETWORK_PORT != port_type) && (SYS_DMPS_MISC_OTHER_PORT != port_type))
        {
            if (!is_cpumac_cal)
            {
                continue;
            }
            else
            {
                /* support cpumac and support misc, loop and eunit for qmgr cal */
                if ((!SYS_USW_IS_CPUMAC_PORT(port_type))
                    && (!((SYS_AT_QMGR_CAL == cal_type) &&
                    ((SYS_AT_IS_MISC_PORT(port_type) || SYS_AT_IS_LOOP_PORT(port_type) ||
                    ((SYS_DMPS_MAX_PORT_TYPE == port_type) &&
                    ((MCHIP_CAP(SYS_CAP_CHANID_EUNIT0) == chan_id) || ((MCHIP_CAP(SYS_CAP_CHANID_EUNIT0) + 1) == chan_id))))))))
                {
                    continue;
                }
            }
        }

        if (1 == index_type)
        {
            index = mac_client_id;
        }
        else
        {
            index = sub_chan_id;
        }

        SYS_AT_SPEED_MODE_TO_SPEED_VALUE(speed_mode, speed);

        /* use 50G speed to calculate calendar, when port is work on 40G-R2*/
        if((CTC_PORT_SPEED_40G == speed_mode) && (CTC_PORT_IF_CR2 == if_type))
        {
            SYS_AT_SPEED_MODE_TO_SPEED_VALUE(SYS_PORT_SPEED_50G, speed);
        }

        if (AT_PP_LEVEL == level)
        {
            index += (dp * SYS_AT_CHAN_NUM_PER_DP);
        }

        cal_info[index].cl_type = SYS_AT_ALLOC_NORMAL;
        cal_info[index].chan_id = sub_chan_id;
        cal_info[index].dport   = dport;
        cal_info[index].speed   = speed;
        cal_info[index].ock     = ock;
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_sub_divisor(uint32 count, uint32 *p_speed, int16 *p_weight, int16 *weight_sum)
{
    uint16 index = 0;
    uint32 val = 0;
    uint32 max = 0;
    uint32 speed = 0;
    uint32 base = 0;
    uint32 common_div = 0;

    sal_memset(p_weight, 0, (sizeof(int16) * count));
    *weight_sum = 0;

    for(index = 0; index < count; index ++)
    {
        speed = *(p_speed + index);
        if(0 != speed)
        {
            max = speed;
            break;
        }
    }

    for(val = 1; val <= max; val ++)
    {
        common_div = 1;
        for(index = 0; index < count; index ++)
        {
            speed = *(p_speed + index);
            if(0 != (speed % val))
            {
                common_div = 0;   /*clear flag*/
                break;
            }
        }

        if(1 == common_div)
        {
            base = val;
        }
    }

    for(index = 0; index < count; index ++)
    {
        speed = *(p_speed + index);
        if((0 != speed) && (0 != base))
        {
            *(p_weight + index) = speed / base;
            *weight_sum += *(p_weight + index);
        }
    }

    return CTC_E_NONE; 
}

int32 
_sys_at_datapath_common_calendar(int16 entry_num, uint32 count, uint32 *p_speed, uint8 *p_error, uint16 *p_walk_end, uint16 *p_cal)
{
    uint16 chan_idx     = 0;
    int16  index        = 0;
    uint16 max_id       = 0;
    int16 weight_sum    = 0;
    int16 max_weight    = 0;
    uint8 high_prio_list[SYS_AT_CHAN_NUM_PER_PP] = {0};
    uint16 en[SYS_AT_CHAN_NUM_PER_PP] = {0};
    int16 *p_weight_list     = NULL;
    int16 *p_weight_list_org = NULL;

    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"entry_num %u, count %u\n", entry_num, count);

    /********************************************
     * common initial phase
     ********************************************/
    p_weight_list = (int16*)mem_malloc(MEM_DMPS_MODULE, count * sizeof(int16));
    if(NULL == p_weight_list)
    {
        return CTC_E_NO_MEMORY;
    }
    sal_memset(p_weight_list, 0, count * sizeof(int16));

    for(chan_idx = 0; chan_idx < count; chan_idx ++)
    {
        en[chan_idx] = (((*(p_speed + chan_idx)) > 0) ? 1 : 0);
    }

    /* calculate divisor */
    _sys_at_datapath_sub_divisor(count, p_speed, p_weight_list, &weight_sum);

    *p_walk_end = weight_sum - 1;
    if(weight_sum > entry_num)
    {
        *p_error = TRUE;
        goto RELEASE_PTR_RETURN;
    }
    else
    {
        *p_error = FALSE;
    }
    
    p_weight_list_org = (int16*)mem_malloc(MEM_DMPS_MODULE, count * sizeof(int16));
    if(NULL == p_weight_list_org)
    {
        goto RELEASE_PTR_RETURN;
    }
    sal_memcpy(p_weight_list_org, p_weight_list, (sizeof(int16) * count));

    for(chan_idx = 0; chan_idx < count; chan_idx++)
    {
        /* if weight greater than 1, then add this port into high priority list */
        high_prio_list[chan_idx] = (p_weight_list[chan_idx] > 1 ? 1 : 0);
    }
    /********************************************
     * common initial phase
     ********************************************/
    for(index = 0; index < weight_sum; index++)
    {
        /* look up max interval */
        max_weight = 0;
        max_id = 0;

        /*1. when there is an elements in the high_prio_list greater than zero,  look up max interval in high_prio_list*/
        for(chan_idx = 0; chan_idx < count; chan_idx ++)
        {
            if(high_prio_list[chan_idx] && en[chan_idx] && (max_weight < p_weight_list[chan_idx]))
            {
                max_weight = p_weight_list[chan_idx];
                max_id = chan_idx;
            }
        }

        /*2. when all elements in the high_prio_list less than zero,  look up max interval in p_weight_list*/
        if(max_weight == 0)
        {
            for(chan_idx = 0; chan_idx < count; chan_idx++)
            {
                if(en[chan_idx] && (max_weight < p_weight_list[chan_idx]))
                {
                    max_weight = p_weight_list[chan_idx];
                    max_id = chan_idx;
                }
            }
        }

        p_cal[index] = max_id;
        
        p_weight_list[max_id] -= weight_sum;

        for(chan_idx = 0; chan_idx < count; chan_idx++)
        {
            if(en[chan_idx])
            {
                p_weight_list[chan_idx] += p_weight_list_org[chan_idx];
            }
        }
    }
    mem_free(p_weight_list_org);

RELEASE_PTR_RETURN:
    mem_free(p_weight_list);

    return CTC_E_NONE; 
}

int32
_sys_at_datapath_epe_netrx_common_calendar(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id,
                                            uint8 is_cpumac_cal, uint8 *p_error, 
                                            uint16 *p_walk_end, uint16 *p_cal, sys_at_cal_info_collect_t* cal_info)
{
    int32  ret                  = CTC_E_NONE;
    uint16 cal_entry_num        = 512;
    uint32 speed                = 0;
    uint32 speed_org            = 0;
    uint32 speed_2nd            = 0;
    uint32 speed_2nd_sum        = 0;
    uint32 speed_2nd_violation  = 0;
    uint32 speed_2nd_sum_max    = 0;
    uint32 index                = 0;
    uint32 *speed_list          = NULL;
    uint32 *speed_list_2nd      = NULL;
    uint16 core_pll             = 0;

    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lchip %u, dp_id %u, is_cpumac_cal %u\n", lchip, dp_id, is_cpumac_cal);

    /********************************************
    * EpeSch common calendar 1st calculate
    ********************************************/
    /*TBD: CPUMAC */
#if 0
    if(is_cpumac_cal)
    {
        mac_id_max += (SYS_AT_CPUMAC_SERDES_NUM / 2);
    }
#endif

    speed_list = (uint32*)mem_malloc(MEM_DMPS_MODULE, SYS_AT_MAX_MAC_CLIENT_PER_DP * sizeof(uint32));
    if(NULL == speed_list)
    {
        return CTC_E_NO_MEMORY;
    }
    sal_memset(speed_list, 0, SYS_AT_MAX_MAC_CLIENT_PER_DP * sizeof(uint32));

    speed_list_2nd = (uint32*)mem_malloc(MEM_DMPS_MODULE, SYS_AT_MAX_MAC_CLIENT_PER_DP * sizeof(uint32));
    if(NULL == speed_list_2nd)
    {
        return CTC_E_NO_MEMORY;
    }
    sal_memset(speed_list_2nd, 0, SYS_AT_MAX_MAC_CLIENT_PER_DP * sizeof(uint32));

    /* stage1 : init speed list */
    for(index = 0; index < SYS_AT_MAX_MAC_CLIENT_PER_DP; index++)
    {
        /*get port speed*/
        speed_org = cal_info[index].speed;

        speed     = speed_org;
        speed_2nd = speed_org;

        //speed     = (((speed_org > 0) && (speed_org < 1)) ? 1 : speed);
        speed_2nd = (((speed_org > 0) && (speed_org < 5)) ? 5 : speed_2nd);

        //speed_list[index]     = ((2 == speed) ? 25 : (speed * 10));       /* 2.5G */
        speed_list[index]     = speed * 10;                /* 2.5G */
        speed_list_2nd[index] = speed_2nd * 10;            /* x.5G */

        speed_2nd_sum += speed_list_2nd[index];
    }

    /* stage2 : violation detect (very important !!!!!! ) */
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1));
    speed_2nd_sum_max = 10 * SYS_AT_DP_BW_MAX * core_pll / SYS_AT_CLK_DEFAULT;
    speed_2nd_violation = ((speed_2nd_sum > speed_2nd_sum_max) ? 1 : 0);

    /* stage3 : calculate calendar use common_calendar */
    if(speed_2nd_violation)
    {
        CTC_ERROR_GOTO(_sys_at_datapath_common_calendar(cal_entry_num, SYS_AT_MAX_MAC_CLIENT_PER_DP,
            speed_list, p_error, p_walk_end, p_cal), 
            ret, RELEASE_PTR_RETURN);
    }
    else
    {
        CTC_ERROR_GOTO(_sys_at_datapath_common_calendar(cal_entry_num, SYS_AT_MAX_MAC_CLIENT_PER_DP,
            speed_list_2nd, p_error, p_walk_end, p_cal), 
            ret, RELEASE_PTR_RETURN);
    }

    /* if PP is empty */
    if(0 == speed_2nd_sum)
    {
        *p_walk_end = 0;
    }

RELEASE_PTR_RETURN:
    mem_free(speed_list);
    mem_free(speed_list_2nd);
    return ret;
}

int32
_sys_at_datapath_calculate_general_calendar_common(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id,
                                                        uint16* cal, uint16* walk_end,
                                                        uint8 is_cpumac_cal, uint8* p_error,
                                                        sys_at_cal_info_collect_t* cal_info)
{
    uint16 i, j;
    uint16 max_id     = 0;
    uint8  chan_idx   = 0;
    int32  max_weight = 0;
    uint32 weight_sum = 0;
    uint8  chan_id_max = SYS_AT_NW_MAC_CLIENT_PER_DP;
    uint16 speed_list[SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)] = {0};
    int32* weight_list = NULL;
    int32* weight_list_org = NULL;
    uint8  en[SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)] = {0};
    uint16 gcd = 0;
    int32  ret = CTC_E_NONE;

    weight_list = mem_malloc(MEM_DMPS_MODULE, sizeof(int32) * (SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)));
    CTC_ERROR_GOTO((NULL == weight_list) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_1);
    sal_memset(weight_list, 0, sizeof(int32) * (SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)));

    weight_list_org = mem_malloc(MEM_DMPS_MODULE, sizeof(int32) * (SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)));
    CTC_ERROR_GOTO((NULL == weight_list_org) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_2);
    sal_memset(weight_list_org, 0, sizeof(int32) * (SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)));

    SYS_USW_VALID_PTR_WRITE(p_error, 0);
    /*TBD: CPUMAC */
#if 0
    if(is_cpumac_cal)
    {
        mac_id_max += (SYS_AT_CPUMAC_SERDES_NUM / 2);
    }
#endif
    /*common initial phase*/
    for(chan_idx = 0; chan_idx < chan_id_max; chan_idx++)
    {
        speed_list[chan_idx] = cal_info[chan_idx].speed * 10;
        en[chan_idx] = (SYS_AT_ALLOC_NONE_MODE == cal_info[chan_idx].cl_type) ? FALSE : TRUE;
    }
    
    /*calculate divisor*/
    CTC_ERROR_GOTO(sys_usw_datapath_get_gcd(speed_list, (SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)), &gcd), 
        ret, RELEASE_PTR_RETURN_3);
    for(chan_idx = 0; chan_idx < chan_id_max; chan_idx++)
    {
        weight_list[chan_idx] = speed_list[chan_idx] / gcd;
        weight_sum += weight_list[chan_idx];
        weight_list_org[chan_idx] = weight_list[chan_idx];
    }

    if(weight_sum > SYS_AT_MAX_CAL_LEN)
    {
        SYS_USW_VALID_PTR_WRITE(p_error, 1);
        ret = CTC_E_NONE;
        goto RELEASE_PTR_RETURN_3;
    }

    /*common calendar main function*/
    for(i = 0; i < weight_sum; i++)
    {
        max_weight = 0;
        max_id = 0;

        /*stage1. look up max interval*/
        for(j = 0; j < chan_id_max; j++)
        {
            if(en[j] && (max_weight < weight_list[j]))
            {
                max_weight = weight_list[j];
                max_id = j;
            }
        }
        cal[i] = max_id;

        /*stage2. common speed list update begin*/
        weight_list[max_id] -= weight_sum;
        for(j = 0; j < chan_id_max; j++)
        {
            if(en[j])
            {
                weight_list[j] += weight_list_org[j];
            }
        }
    }

    SYS_USW_VALID_PTR_WRITE(walk_end, (weight_sum-1));
    SYS_USW_VALID_PTR_WRITE(p_error, 0);
    
RELEASE_PTR_RETURN_3:
    mem_free(weight_list_org);
RELEASE_PTR_RETURN_2:
    mem_free(weight_list);
RELEASE_PTR_RETURN_1:
    return ret;
}

int32
_sys_at_dp_calculate_interval(uint8 lchip, uint32 speed, uint32 num, uint8 low_prio, uint8 extra,
                               uint8 is_tx, uint32 bw_ratio, uint32* interval, uint32* p_cnt_sum)
{
    uint32 cnt = 0;
    uint32 avg_base = 0;
    uint32 avg_new = 0;
    uint32 cnt_org = 0;
    uint32 cnt_org_a1 = 0;
    uint32 cnt_sum = 0;
    uint32 cnt_sum_chg = 0;
    uint16 core_pll = 0;

    (void) sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1);

    if(speed != 0)
    {
        if(is_tx)
        {
            /* division not at the end of the  expression wiil loss some accuracy */
            avg_base = bw_ratio * ((SYS_AT_MAC_CALENDAR_BUS_WIDTH_TX*1 + 20 + 1)*8 ) * core_pll / (2 * 1000 * speed);
        }
        else
        {
            avg_base = bw_ratio * ((SYS_AT_MAC_CALENDAR_BUS_WIDTH_EPE+20) * 8 ) * core_pll / (speed*1000);
        }
    }
    else
    {
        *interval = 0;
        return CTC_E_NONE;
    }

    cnt_org = avg_base / SYS_AT_MAC_CALENDAR_MULTI_FACTOR;
    cnt_org_a1 = is_tx ? (cnt_org + 1) : cnt_org;

    if(low_prio || extra)
    {
        cnt = cnt_org_a1;
    }
    else if(num != 1)
    {
        cnt_sum = *p_cnt_sum;
        cnt_sum_chg = cnt_sum + cnt_org_a1;
        avg_new = (cnt_sum_chg * SYS_AT_MAC_CALENDAR_MULTI_FACTOR) / num;
        cnt = (avg_new > avg_base) ? cnt_org : cnt_org_a1;
    }
    else
    {
        cnt = cnt_org;
    }

    *interval = cnt;
    *p_cnt_sum = cnt + cnt_sum;

    return CTC_E_NONE;
}


int32
_sys_at_datapath_calculate_general_calendar(uint8 lchip, uint8 optimize_cal, uint8 core_id, uint8 pp_id, uint8 dp_id, 
                                                uint16* cal_epe, uint16* walk_end_epe, uint8 is_cpumac_cal, 
                                                uint8* p_error, uint32 mind_depth, sys_at_cal_info_collect_t* cal_info)
{
    uint8 txqm_id_0 = 0;
    uint8 p = 0;

    uint8 txqm_record = 0;
    uint16 speed_f = 0;

    uint8  mac_id_max = SYS_AT_NW_MAC_CLIENT_PER_DP;
    uint32* interval = NULL;/*interval,per port*/
    uint32* interval_cp = NULL;/*interval,per port*/
    uint32* interval_order = NULL;/*interval,per port*/
    uint16 portid_order[SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)] = {0};/*interval,per port*/
    uint32* num = NULL;/*select num ,per port*/
    uint8  active[SYS_AT_NW_MAC_CLIENT_PER_DP+1 + (SYS_AT_CPUMAC_SERDES_NUM / 2)] = {0};/*active list*/
    uint8  en[SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)] = {0};/*port enable*/
    uint16 first_cal_record[SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)] = {0};/*record the index first select*/
    uint8  first_cal_record_en[SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)] = {0};/*record the index first select*/
    uint32 speed_sum = 0;
    uint32 speed = 0;
    uint32 oversub_bw = 1400;
    uint8  oversub_flag = FALSE;
    uint32 member_num = 0;
    uint32  bw_ratio = 1000;
    /*uint8  spd_2nd_flag = FALSE;*/
    uint8  spd_2nd_lock = 0;
    uint8  spd_max_lock = 0;
    uint8  low_prio = FALSE;
    uint16 cycle    = 0;  /*calendar cycle*/
    uint8  done     = FALSE;
    /*uint8  error    = FALSE;*/
    /*uint8  force_sel = FALSE;*/
    uint16 min_id = 1;
    uint32 min_intv = 10000;
    uint16 min_index = 0;
    uint8  exchange_flag = 0;
    uint32 selport = 0;
    uint8  extra = FALSE;
    uint8  active_flag = FALSE;
    uint8  illegal = FALSE;
    uint8  reload_active = FALSE;
    /*uint8  mactx_illegal = 0;*/
    uint8  i, k;
    
    uint32 actual_interval = 0;
    uint32 expect_interval = 0;
    uint32 multi_factor = 1000;
    uint32 speed_diff = 0;
    uint8 find_same_speed = FALSE;
    uint32 diff_speed_num = 0;
    uint32* speed_record = NULL;
    uint32 max_id;
    uint32 max_speed;
    uint32* speed_order = NULL;
    uint8 force_sel_epe = FALSE;
    uint8 force_sel = FALSE;

    uint32 last_gap = 0;
    uint16 mac_id;
    uint16 mac_id_tmp;
    uint32* cnt_history = NULL;
    uint8 txqm_RR = 0;
    
    uint32 speed_rate = 1;
    uint32 num_rate = 1;
    uint32 op_round = 1;
    uint32 speed_1st_num = 0;
    uint32 speed_2nd_num = 0;
    uint32 speed_1st = 0;
    uint32 speed_2nd;
    uint16 ooo;
    uint32 speed_ooo;
    uint32 speed_tx;
    int32  ret = CTC_E_NONE;
    uint16 core_pll = 0;

    (void) sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1);
 
    /*per-txqm operation*/
    
    done = FALSE;
    /*error = FALSE;*/
    cycle = 0;
    speed_sum = 0;
    speed = 0;
    oversub_flag = FALSE;
    member_num = 0;
    bw_ratio = 1000;

    *p_error = 0;

    /* TBD: CPUMAC */
#if 0
    if(is_cpumac_cal)
    {
        mac_id_max += (SYS_AT_CPUMAC_SERDES_NUM / 2);
    }
#endif
    interval = (uint32*)mem_malloc(MEM_DMPS_MODULE, (SYS_AT_NW_MAC_CLIENT_PER_DP+(SYS_AT_CPUMAC_SERDES_NUM / 2)) * sizeof(uint32));
    CTC_ERROR_GOTO((NULL == interval) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_1);
    sal_memset(interval, 0, (SYS_AT_NW_MAC_CLIENT_PER_DP+(SYS_AT_CPUMAC_SERDES_NUM / 2)) * sizeof(uint32));

    interval_cp = (uint32*)mem_malloc(MEM_DMPS_MODULE, (SYS_AT_NW_MAC_CLIENT_PER_DP + 1 + (SYS_AT_CPUMAC_SERDES_NUM / 2)) * sizeof(uint32));
    CTC_ERROR_GOTO((NULL == interval_cp) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_2);
    sal_memset(interval_cp, 0, (SYS_AT_NW_MAC_CLIENT_PER_DP + 1 + (SYS_AT_CPUMAC_SERDES_NUM / 2)) * sizeof(uint32));

    interval_order = (uint32*)mem_malloc(MEM_DMPS_MODULE, (SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)) * sizeof(uint32));
    CTC_ERROR_GOTO((NULL == interval_order) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_3);
    sal_memset(interval_order, 0, (SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)) * sizeof(uint32));

    num = (uint32*)mem_malloc(MEM_DMPS_MODULE, (SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)) * sizeof(uint32));
    CTC_ERROR_GOTO((NULL == num) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_4);
    sal_memset(num, 0, (SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)) * sizeof(uint32));

    speed_order = (uint32*)mem_malloc(MEM_DMPS_MODULE, (SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)) * sizeof(uint32));
    CTC_ERROR_GOTO((NULL == speed_order) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_5);
    sal_memset(speed_order, 0, (SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)) * sizeof(uint32));

    cnt_history = (uint32*)mem_malloc(MEM_DMPS_MODULE, (SYS_AT_MAX_CHAN_NUM) * sizeof(uint32));
    CTC_ERROR_GOTO((NULL == cnt_history) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_6);
    sal_memset(cnt_history, 0, (SYS_AT_MAX_CHAN_NUM) * sizeof(uint32));

    speed_record = (uint32*)mem_malloc(MEM_DMPS_MODULE, (SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)) * sizeof(uint32));
    CTC_ERROR_GOTO((NULL == speed_record) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_7);
    sal_memset(speed_record, 0, (SYS_AT_NW_MAC_CLIENT_PER_DP + (SYS_AT_CPUMAC_SERDES_NUM / 2)) * sizeof(uint32));

    /*initial phase*/
    for(i = 0; i < mac_id_max; i++)
    {
        mac_id = i;
        SYS_CONDITION_CONTINUE(SYS_AT_ALLOC_NONE_MODE == cal_info[mac_id].cl_type);
        speed = cal_info[mac_id].speed;
        speed_sum += speed;
        first_cal_record[i] = 0;
        first_cal_record_en[i] = TRUE;
    }

    if(speed_sum > oversub_bw)
    {
        oversub_flag = 1;
    }
    /*else
    {
        bw_ratio = speed_sum*1000 / 1400;
    }*/

    /*look up low priority speed, inherit from Duet2*/
    /*spd_2nd_flag = FALSE;*/
    spd_2nd_lock = 0;
    spd_max_lock = 0;

    for(i = 0; i < mac_id_max; i++)
    {
        mac_id = i;
        SYS_CONDITION_CONTINUE(SYS_AT_ALLOC_NONE_MODE == cal_info[mac_id].cl_type);
        speed_f = cal_info[mac_id].speed;
        
        if((speed_f != 0) && (speed_f > spd_max_lock))
        {
            spd_2nd_lock = spd_max_lock;
            spd_max_lock = speed_f;
        }

        if((speed_f != 0) && (speed_f > spd_2nd_lock) && (speed_f < spd_max_lock))
        {
            spd_2nd_lock = speed_f;
        }
    }

    /*look up different speed. for calendar optimization*/
    for(i = 0; i < mac_id_max; i++)
    {
        mac_id = i;
        SYS_CONDITION_CONTINUE(SYS_AT_ALLOC_NONE_MODE == cal_info[mac_id].cl_type);
        speed_diff = cal_info[mac_id].speed;
        find_same_speed = FALSE;

        if(0 != speed_diff)
        {
            if(0 == diff_speed_num)
            {
                speed_record[0] = speed_diff;
                diff_speed_num++;
            }
            else
            {
                for(k = 0; k < diff_speed_num; k++)
                {
                    if(speed_record[k] == speed_diff)
                    {
                        find_same_speed = TRUE;
                    }
                }
                if(!find_same_speed)
                {
                    speed_record[diff_speed_num] = speed_diff;
                    diff_speed_num++;
                }
            }
        }
    }
    /*EPE speed array bubble sort begin*/
    for(k = 0; k < diff_speed_num; k++)
    {
        max_id = 1;
        max_speed = 0;
        for(i = 0; i < mac_id_max; i++)
        {
            if(max_speed < speed_record[i])
            {
                max_speed = speed_record[i];
                max_id = i;
            }
        }
        speed_record[max_id] = 0;
        speed_order[k] = max_speed;
    }
    
    for(i = 0; i < mac_id_max; i++)
    {
        mac_id = i;
        SYS_CONDITION_CONTINUE(SYS_AT_ALLOC_NONE_MODE == cal_info[mac_id].cl_type);
        speed = cal_info[mac_id].speed;
        
        low_prio = oversub_flag && (spd_max_lock != speed);
        /*initial interval*/
        _sys_at_dp_calculate_interval(lchip, speed, 1, low_prio, 0, 0, 
                                       bw_ratio, interval + i, &(cnt_history[mac_id]));
        /*initial active / enable and num*/
        if(1 <= speed)
        {
            active[i] = TRUE;
            en[i] = TRUE;
            num[i] = 1;
            member_num++;
        }
        else  /*invalid port*/
        {
            active[i] = FALSE;
            en[i] = FALSE;
            num[i] = 1;
            //member_num++;
        }
    }

    /*main function*/
    while((!done) && (!(*p_error)))
    {
        /*reorder*/
        for(i = 1; i <= mac_id_max; i++)
        {
            interval_cp[i] = interval[i-1];
        }
        /*stage1. bubble sort*/
        for(i = 1; i <= member_num; i++)
        {
            min_id = 1;
            min_intv = 10000;
            
            for(k = 1; k <= mac_id_max; k++)
            {
                if((interval_cp[k]) && (min_intv > interval_cp[k]))
                {
                    min_intv = interval_cp[k];
                    min_id = k;
                }
                else if((interval_cp[k]) && (min_intv == interval_cp[k]) && active[k])
                {
                    min_id = k;
                }
            }
            interval_cp[min_id] = 10000;
            interval_order[i] = min_intv;
            portid_order[i] = min_id - 1;
        }

        /*stage2. calendar select*/
        min_index = portid_order[1];  /*default min interval portid*/
        min_intv = interval_order[1];  /*default min interval*/
        /*detect error*/
        /*force_sel = FALSE;*/
        exchange_flag = FALSE;
        txqm_RR = (txqm_record == 3) ? 0 : txqm_record + 1;
        for(txqm_id_0 = 0; txqm_id_0 < 4; txqm_id_0++)
        {
            uint8 force_sel_txqm = 0;

            for(i = 1; i <= member_num; i++)
            {
               if(i > interval_order[i])
               {
                    *p_error = 2;
                    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, 
                        "%% [general]automatic constrain failed! failed id = %u, interval = %u, cycle = %u\n", i, 
                        interval_order[i], cycle);
                    for(k = 1; k <= member_num; k++)
                    {
                        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% [general]bubble sort index %u, interval %u\n", 
                            k, interval_order[k]);
                    }
                    break;
                } 
                /*get the mac id*/
                selport = portid_order[i];
                /*exchange min_index due to : 
                1: must in active list 
                2: doesn't set exchange_flag before 
                3: doesn't set force_sel before 
                4: has small interval*/
                if((active[selport]) && (!exchange_flag) && (!force_sel_txqm) && ((selport / 40) == txqm_RR))
                {
                    min_index = portid_order[i];
                    exchange_flag = TRUE;
                    min_intv = interval_order[i];
                }
            /*force_sel eq 1 means calendar can't select the portid_order index larger than i*/
                if(i == interval_order[i])
                {
                    /*force_sel = TRUE;*/
                    force_sel_txqm = TRUE;
                }
            }

            txqm_RR = (txqm_RR == 3) ? 0 : txqm_RR + 1;
        }

        /*stage2.2 loop up minIndex without TXQM RR condition*/
        force_sel_epe = 0;
        for(i = 1; i <= member_num; i++)
        {
            selport = portid_order[i];
            
            /*exchange minIndex due to : */
            /*1: must in active list */
            /*2: doesn't set exchange_flag before (may be assert by step2.1 and step2.2)*/
            /*3: doesn't set force_sel before */
            /*4: has small interval*/
            if(active[selport] && (!exchange_flag) && (!force_sel_epe))  /*epe calendar chg flag*/
            {
                min_index = portid_order[i];
                exchange_flag = TRUE;
                min_intv = interval_order[i];
            }
            /*if $force_sel_epe eq 1 ,means calendar can't select the portid_order index larger than i */
            if(i == interval_order[i])
            {
                force_sel = TRUE;
                force_sel_epe = TRUE; /*epe calendar chg flag*/
            }
        }

        /*stage3. maintain DS*/
        txqm_record = min_index / 40;
        /*stage3.1 all interval will decrease 1*/
        for(i = 0; i < mac_id_max; i++)
        {
            if(en[i])
            {
                interval[i]--;
            }
        }
        /*stage3.2 generage calendar data*/
        //cal[j][cycle] = min_index;
        cal_epe[cycle] = min_index;

        /*stage3.3  re-calulate interval*/
        mac_id = min_index;
        SYS_CONDITION_CONTINUE(SYS_AT_ALLOC_NONE_MODE == cal_info[mac_id].cl_type);
        speed = cal_info[mac_id].speed;
        extra = (min_intv > 1) && force_sel;

        low_prio = oversub_flag && (spd_max_lock != speed);
        _sys_at_dp_calculate_interval(lchip, speed, num[min_index], low_prio, extra, 0, 
                                       bw_ratio, interval + min_index, &(cnt_history[mac_id]));
        num[min_index]++;  /*num++ after re-calculate interval*/
        active[min_index] = FALSE;

        /*stage3.4 record the first calendar cycle*/
        if(first_cal_record_en[min_index])
        {
            first_cal_record[min_index] = cycle;
            first_cal_record_en[min_index] = FALSE;
        }

        /*stage4. finish calendar calculate*/
        /*4.1 detect active flag*/
        active_flag = FALSE;
        
        for(i = 0; i < mac_id_max; i++)
        {
            if(active[i])
            {
                active_flag = TRUE;
            }
        }
        /*4.2 detect interval violation*/
        /*NetTx use 1*192+1 Byte to calculate interval average*/
        if(!active_flag)
        {
            /*uint8 high_speed_num = 0;
            uint8 low_speed_num = 0;*/
                
            illegal = FALSE;
            /*mactx_illegal = 0;*/
            /*sal_memset(mactx_reorder_en, FALSE, SYS_TMM_MAX_MAC_NUM_PER_DP*sizeof(uint8));*/
            for(i = 0; i < mac_id_max; i++)
            {
                mac_id = i;
                SYS_CONDITION_CONTINUE(SYS_AT_ALLOC_NONE_MODE == cal_info[mac_id].cl_type);
                speed_tx = cal_info[mac_id].speed;

                /*if(speed_tx == spd_max_lock)
                    high_speed_num = num[i] - 1;
                if(speed_tx == spd_2nd_lock)
                    low_speed_num = num[i] - 1;*/

                /*port enable*/
                if(0 != speed_tx)
                {
                    /*192*1+1 B could reach performance*/
                    expect_interval = ((SYS_AT_MAC_CALENDAR_BUS_WIDTH_EPE+20) * core_pll * 8) / speed_tx;
                    actual_interval = (((uint32)cycle + 1) * multi_factor) / (num[i] - 1);
                    if(actual_interval > expect_interval)
                    {
                        illegal = TRUE;
                        active[i] = TRUE;
                    }
                    /*tail --> head gap illegal calculate*/
                    /*last_gap = first_cal_record[i];*/
                    last_gap = (first_cal_record[i] > 1) ? (first_cal_record[i] - 1) : 0;
                    last_gap = last_gap * bw_ratio / multi_factor;
                    if(last_gap > interval[i])
                    {
                        /*illegal = TRUE;
                        active[i] = TRUE;*/
                    }
                }
            }

            if(optimize_cal)
            {
                speed_rate = 1;
                num_rate = 1;
                op_round = 1;
                speed_1st_num = 0;
                speed_2nd_num = 0;

                if(1 < diff_speed_num)
                {
                    uint32 loop_cycle_max = (mind_depth > diff_speed_num) ? diff_speed_num : mind_depth;

                    for(op_round = 0; op_round <= loop_cycle_max-2; op_round++)
                    {
                        if(op_round == 0)
                        {
                            speed_1st = speed_order[op_round];
                        }
                        speed_2nd = speed_order[op_round+1];

                        for(ooo = 0; ooo < mac_id_max; ooo++)
                        {
                            mac_id_tmp = ooo;
                            SYS_CONDITION_CONTINUE(SYS_AT_ALLOC_NONE_MODE == cal_info[mac_id_tmp].cl_type);
                            speed_ooo = cal_info[mac_id_tmp].speed;

                            if(speed_ooo == speed_1st)
                            {
                                speed_1st_num = num[ooo] - 1;
                            }
                            if(speed_ooo == speed_2nd)
                            {
                                speed_2nd_num = num[ooo] - 1;
                            }
                        }

                        SYS_CONDITION_CONTINUE((0 == speed_2nd) || (0 == speed_2nd_num));
                        speed_rate = 10 * speed_1st / speed_2nd;
                        num_rate = 10 * speed_1st_num / speed_2nd_num;

                        if(speed_rate > num_rate)
                        {
                            illegal = TRUE;
                            for(p = 0; p < mac_id_max; p++)
                            {
                                mac_id_tmp = p;
                                SYS_CONDITION_CONTINUE(SYS_AT_ALLOC_NONE_MODE == cal_info[mac_id_tmp].cl_type);
                                speed_tx = cal_info[mac_id_tmp].speed;
                                if(speed_tx == speed_1st)
                                {
                                    active[p] = TRUE;
                                }
                            }
                            speed_1st = speed_2nd;
                        }
                        else if(speed_rate < num_rate)
                        {
                            illegal = TRUE;
                            for(p = 0; p < mac_id_max; p++)
                            {
                                mac_id_tmp = p;
                                SYS_CONDITION_CONTINUE(SYS_AT_ALLOC_NONE_MODE == cal_info[mac_id_tmp].cl_type);
                                speed_tx = cal_info[mac_id_tmp].speed;
                                if(speed_tx == speed_2nd)
                                {
                                    active[p] = TRUE;
                                }
                            }
                        }
                        else
                        {
                            speed_1st = speed_2nd;
                        }
                    }
                }
            }

            reload_active = illegal;
            /*finish if no violation*/
            if(!reload_active)
            {
                done = TRUE;
                *walk_end_epe = cycle;
            }
        }
        cycle++;
        if(cycle >= SYS_AT_MAX_CAL_LEN)
        {
            *p_error = 1;
        }
    }

    if(*p_error)
    {
        ret = CTC_E_INVALID_PARAM;
        goto RELEASE_PTR_RETURN_8;
    }
    
RELEASE_PTR_RETURN_8:
    mem_free(speed_record);
RELEASE_PTR_RETURN_7:
    mem_free(cnt_history);
RELEASE_PTR_RETURN_6:
    mem_free(speed_order);
RELEASE_PTR_RETURN_5:
    mem_free(num);
RELEASE_PTR_RETURN_4:
    mem_free(interval_order);
RELEASE_PTR_RETURN_3:
    mem_free(interval_cp);
RELEASE_PTR_RETURN_2:
    mem_free(interval);
RELEASE_PTR_RETURN_1:
    return ret;
}


int32
_sys_at_datapath_calculate_general_calendar_parser(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 is_cpumac_cal,
                                                    uint16* cal, uint16* walk_end, sys_at_cal_info_collect_t* cal_info)
{
    uint32 mind_depth[] = {10, 3, 3};
    uint8  optimize_cal[] = {1, 1, 0};
    uint8  idx;
    uint8  error = TRUE;

    /*1. First Use new calendar algorithms*/
    sal_memset(cal, 0, SYS_AT_MAX_CAL_LEN * sizeof(uint16));
    *walk_end = 0;

    /*If don't calculation, then use old common calculation*/
    _sys_at_datapath_epe_netrx_common_calendar(lchip, core_id, pp_id, dp_id, is_cpumac_cal, &error, walk_end, cal, cal_info);
    if(!error)
    {
        return CTC_E_NONE;
    }

    sal_memset(cal, 0, SYS_AT_MAX_CAL_LEN * sizeof(uint16));
    *walk_end = 0;
    _sys_at_datapath_calculate_general_calendar_common(lchip, core_id, pp_id, dp_id, cal, walk_end, is_cpumac_cal, &error, cal_info);

    /*then try 3 times at most*/
    for(idx = 0; idx < 3; idx++)
    {
        sal_memset(cal, 0, SYS_AT_MAX_CAL_LEN * sizeof(uint16));
        *walk_end = 0;
        error = 0;
        _sys_at_datapath_calculate_general_calendar(lchip, optimize_cal[idx], core_id, pp_id, dp_id, cal, walk_end, is_cpumac_cal, 
                                                     &error, mind_depth[idx], cal_info);
        if(!error)
        {
            return CTC_E_NONE;
        }
    }

    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% Calculation of general calendar (%s cpumac) error! core_id %d pp_id %d dp_id %d\n", 
        (is_cpumac_cal ? "with" : "no"), core_id, pp_id, dp_id);
    return CTC_E_INVALID_PARAM;
}

int32
_sys_at_datapath_epe_calendar_write_to_register(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id,
                                                    const uint16* cal, uint16 walk_end)
{
    uint8  is_back_cal = 0;
    uint16 i       = 0;
    uint32 val_32  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    EpeScheduleCalendar0Ram_m epe_cal;
    EpeScheduleCalCtl_m cal_ctl;

//EpeScheduleCalCtl---
    index = DRV_INS(0, 0);
    
    cmd = DRV_IOR(EpeScheduleCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &cal_ctl));

    val_32 = GetEpeScheduleCalCtl(V, cfgCalUsedEn_f, &cal_ctl);
    is_back_cal = GetEpeScheduleCalCtl(V, cfgCalSelPtr_f, &cal_ctl);
    if(val_32 == 0)
        is_back_cal = 0;
    else 
        is_back_cal = is_back_cal ? 0 : 1;

//EpeScheduleCalendar[0 1]Ram ---
    /* Entry */
    tbl_id = (is_back_cal ? EpeScheduleCalendar1Ram_t : EpeScheduleCalendar0Ram_t);
    fld_id = (is_back_cal ? EpeScheduleCalendar1Ram_calPtr_f : EpeScheduleCalendar0Ram_calPtr_f);
    for(i = 0; i <= walk_end; i++)
    {       
        index = DRV_INS(0, i);

        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &epe_cal));

        /* TBD: CPUmac */
        //val_32 = (cal[i] >= SYS_AT_NW_MAC_CLIENT_PER_DP) ? (cal[i]+2) : cal[i];
        val_32 = cal[i];
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, i, fld_id, &val_32, &epe_cal);

        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &epe_cal));
    }

    /* WalkerEnd */
    val_32 = walk_end;
    if(is_back_cal)
    {
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, EpeScheduleCalCtl_t, 0, 0, EpeScheduleCalCtl_cfgCal1WalkEndPtr_f, &val_32, &cal_ctl);
    }
    else
    {
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, EpeScheduleCalCtl_t, 0, 0, EpeScheduleCalCtl_cfgCal0WalkEndPtr_f, &val_32, &cal_ctl);
    }
    index = DRV_INS(0, 0);
    cmd = DRV_IOW(EpeScheduleCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &cal_ctl));

    /* BankSel */
    cmd = DRV_IOR(EpeScheduleCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &cal_ctl));
    val_32 = 1;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, EpeScheduleCalCtl_t, 0, 0, EpeScheduleCalCtl_cfgCalUsedEn_f, &val_32, &cal_ctl);
    val_32 = is_back_cal;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, EpeScheduleCalCtl_t, 0, 0, EpeScheduleCalCtl_cfgCalSelPtr_f, &val_32, &cal_ctl);
    cmd = DRV_IOW(EpeScheduleCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &cal_ctl));

    return CTC_E_NONE;
}

/* 
 * @note        -outDataCalEnable_f initial value is 1
 *              so is_back_cal checking is not working.
 *              this also means we will write to Calendar1Mem at the first time.
 *              -index by CHANNEL ID
 */
int32
_sys_at_datapath_bufretrv_calendar_write_to_register(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id,
                                                        const uint16* cal, uint16 walk_end)
{
    uint8  is_back_cal   = 0;
    uint8  core          = 0;
    uint16 i             = 0;
    uint32 val_32        = 0;
    uint32 index         = 0;
    uint32 cmd           = 0;
    uint32 table_out_cal = 0;
    uint32 table_buf_cal = 0;
    uint32 field_out_cal = 0;
    uint32 field_buf_cal = 0;
    PreBrBufPtrCalendar0Mem_m   buf_cal;
    PostBrOutDataCalendar0Mem_m out_cal;
    PreBrWrrCtl_m               pre_ctl;
    PostBrWrrCtl_m              post_ctl;
    BufRetrvDPWrrCtl_m          br_ctl;

    index = DRV_INS(0, 0);

    cmd = DRV_IOR(BufRetrvDPWrrCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &br_ctl));

    val_32 = GetBufRetrvDPWrrCtl(V, outDataCalEnable_f, &br_ctl);
    is_back_cal = GetBufRetrvDPWrrCtl(V, bufPtrCalSel_f, &br_ctl);
    if(val_32 == 0)
    {
        is_back_cal = 0;
    }
    else
    {
        is_back_cal = is_back_cal ? 0 : 1;
    }

    /* Entry */
    if(is_back_cal)
    {
        table_out_cal = PostBrOutDataCalendar1Mem_t;
        table_buf_cal = PreBrBufPtrCalendar1Mem_t;
        field_out_cal = PostBrOutDataCalendar1Mem_chanId_f;
        field_buf_cal = PreBrBufPtrCalendar1Mem_chanId_f;
    }
    else
    {
        table_out_cal = PostBrOutDataCalendar0Mem_t;
        table_buf_cal = PreBrBufPtrCalendar0Mem_t;
        field_out_cal = PostBrOutDataCalendar0Mem_chanId_f;
        field_buf_cal = PreBrBufPtrCalendar0Mem_chanId_f;
    }

    for(i = 0; i <= walk_end; i++)
    {
        /* PostBrOutDataCalendarMem */
        index = DRV_INS(0, i);
        cmd   = DRV_IOR(table_out_cal, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &out_cal));

        val_32 = cal[i];
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, table_out_cal, 0, i, field_out_cal, &val_32, &out_cal);

        cmd = DRV_IOW(table_out_cal, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &out_cal));

        /* local core */
        core  = core_id;
        /* PreBrBufPtrCalendarMem */
        index = DRV_INS(0, i);
        cmd   = DRV_IOR(table_buf_cal, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &buf_cal));

        val_32 = cal[i];
        DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, table_buf_cal, 0, i, field_buf_cal, &val_32, &buf_cal);

        cmd = DRV_IOW(table_buf_cal, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &buf_cal));

        if (SYS_AT_CHIP_IS_DC(lchip))
        {
            /* remote core */
            core  = (0 == core_id) ? 1 : 0;
            /* PreBrBufPtrCalendarMem */
            index = DRV_INS(1, i);
            cmd   = DRV_IOR(table_buf_cal, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &buf_cal));

            val_32 = cal[i];
            DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, table_buf_cal, 1, i, field_buf_cal, &val_32, &buf_cal);

            cmd = DRV_IOW(table_buf_cal, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &buf_cal));
        }
    }

    /* local core */
    core  = core_id;
    index = DRV_INS(0, 0);

    cmd = DRV_IOR(PreBrWrrCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pre_ctl));

    cmd = DRV_IOR(PostBrWrrCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &post_ctl));

    /* WalkerEnd */
    if(is_back_cal)
    {
        val_32 = walk_end;
        DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrWrrCtl_t,  0, 0, PreBrWrrCtl_bufPtrCalWalkEndPtr1_f,   &val_32, &pre_ctl);
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, PostBrWrrCtl_t, 0, 0, PostBrWrrCtl_outDataCalWalkEndPtr1_f, &val_32, &post_ctl);
    }
    else
    {
        val_32 = walk_end;
        DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrWrrCtl_t,  0, 0, PreBrWrrCtl_bufPtrCalWalkEndPtr0_f,   &val_32, &pre_ctl);
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, PostBrWrrCtl_t, 0, 0, PostBrWrrCtl_outDataCalWalkEndPtr0_f, &val_32, &post_ctl);
    }

    /* WrrCtl */
    val_32 = 1;
    DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrWrrCtl_t,  0, 0, PreBrWrrCtl_bufPtrCalEnable_f,   &val_32, &pre_ctl);
    val_32 = is_back_cal;
    DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrWrrCtl_t,  0, 0, PreBrWrrCtl_bufPtrCalSel_f,      &val_32, &pre_ctl);
    val_32 = 1;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, PostBrWrrCtl_t, 0, 0, PostBrWrrCtl_outDataCalEnable_f, &val_32, &post_ctl);
    val_32 = is_back_cal;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, PostBrWrrCtl_t, 0, 0, PostBrWrrCtl_outDataCalSel_f,    &val_32, &post_ctl); 

    cmd = DRV_IOW(PreBrWrrCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pre_ctl));

    cmd = DRV_IOW(PostBrWrrCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &post_ctl));

    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        /* remote core */
        core  = (0 == core_id) ? 1 : 0;
        index = DRV_INS(1, 0);

        cmd = DRV_IOR(PreBrWrrCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pre_ctl));

        /* WalkerEnd */
        if(is_back_cal)
        {
            val_32 = walk_end;
            DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrWrrCtl_t,  1, 0, PreBrWrrCtl_bufPtrCalWalkEndPtr1_f,   &val_32, &pre_ctl);
        }
        else
        {
            val_32 = walk_end;
            DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrWrrCtl_t,  1, 0, PreBrWrrCtl_bufPtrCalWalkEndPtr0_f,   &val_32, &pre_ctl);
        }

        /* WrrCtl */
        val_32 = 1;
        DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrWrrCtl_t,  1, 0, PreBrWrrCtl_bufPtrCalEnable_f,   &val_32, &pre_ctl);
        val_32 = is_back_cal;
        DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrWrrCtl_t,  1, 0, PreBrWrrCtl_bufPtrCalSel_f,      &val_32, &pre_ctl);

        cmd = DRV_IOW(PreBrWrrCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pre_ctl));
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_netrx_calendar_write_to_register(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id,
                                                    const uint16* cal, uint16 walk_end)
{
    uint8 is_back_cal = 0;
    uint16 i       = 0;
    uint32 val_32  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    NetRxCalendar0_m netrx_cal;
    NetRxCalCtl_m cal_ctl;

//NetRxCalCtl---
    index = DRV_INS(0, 0);
    
    cmd = DRV_IOR(NetRxCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &cal_ctl));

    val_32 = GetNetRxCalCtl(V, cfgCalUsedEn_f, &cal_ctl);
    is_back_cal = GetNetRxCalCtl(V, cfgCalSel_f, &cal_ctl);
    if(val_32 == 0)
        is_back_cal = 0;
    else
        is_back_cal = is_back_cal ? 0 : 1;

//NetRxCalendar ---
    /* entry */
    tbl_id = (is_back_cal ? NetRxCalendar1_t : NetRxCalendar0_t);
    fld_id = (is_back_cal ? NetRxCalendar1_port_f : NetRxCalendar0_port_f);
    for(i = 0; i <= walk_end; i++)
    {       
        index = DRV_INS(0, i);
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &netrx_cal));

        val_32 = cal[i];
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, i, fld_id, &val_32, &netrx_cal);

        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &netrx_cal));
    }

    /* WalkerEnd */
    val_32 = walk_end;
    if(is_back_cal)
    {
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetRxCalCtl_t, 0, 0, NetRxCalCtl_cfgCal1WalkEndPtr_f, &val_32, &cal_ctl);
    }
    else
    {
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetRxCalCtl_t, 0, 0, NetRxCalCtl_cfgCal0WalkEndPtr_f, &val_32, &cal_ctl);
    }

    index = DRV_INS(0, 0);
    cmd = DRV_IOW(NetRxCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &cal_ctl));

    /* BankSel */
    cmd = DRV_IOR(NetRxCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &cal_ctl));

    val_32 = 1;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetRxCalCtl_t, 0, 0, NetRxCalCtl_cfgCalUsedEn_f, &val_32, &cal_ctl);
    val_32 = is_back_cal;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetRxCalCtl_t, 0, 0, NetRxCalCtl_cfgCalSel_f, &val_32, &cal_ctl);

    cmd = DRV_IOW(NetRxCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &cal_ctl));

    return CTC_E_NONE;
}


int32
_sys_at_datapath_set_general_calendar(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 dir_bmp)
{
    int32  ret = CTC_E_NONE;
    uint16* cal = NULL;
    uint16 walk_end = 0;
    sys_at_cal_info_collect_t* cal_info = NULL;

    cal = (uint16*)mem_malloc(MEM_DMPS_MODULE, SYS_AT_MAX_CAL_LEN * sizeof(uint16));
    CTC_ERROR_GOTO((NULL == cal) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_1);
    sal_memset(cal, 0xff, SYS_AT_MAX_CAL_LEN * sizeof(uint16));

    cal_info = (sys_at_cal_info_collect_t*)mem_malloc(MEM_DMPS_MODULE,
        SYS_AT_CHAN_NUM_PER_PP * sizeof(sys_at_cal_info_collect_t)); /* mac_client_id = 32: cpumac */
    CTC_ERROR_GOTO((NULL == cal_info) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_2);

    if (CHAN_DIR_IS_TX(dir_bmp))
    {
        /* 1.  set EPE calendar, consider CPUMAC */
        /* 1.1 info collect */
        _sys_at_calendar_speed_info_collect(lchip, cal_info, core_id, pp_id, dp_id, DMPS_INVALID_VALUE_U8, SYS_AT_EPE_CAL);
        /* 1.2 calender caculateion */
        CTC_ERROR_GOTO(_sys_at_datapath_calculate_general_calendar_parser(lchip, core_id, pp_id, dp_id, TRUE, cal, &walk_end, cal_info), 
            ret, RELEASE_PTR_RETURN_3);
        /* 1.3 config register */
        if(SYS_AT_MAX_CAL_LEN > walk_end)
        {
            CTC_ERROR_GOTO(_sys_at_datapath_epe_calendar_write_to_register(lchip, core_id, pp_id, dp_id, cal, walk_end), 
                ret, RELEASE_PTR_RETURN_3);
        }

        /* 2.  set BufRetrv calender, consider CPUMAC */
        /* 2.1 info collect */
        _sys_at_calendar_speed_info_collect(lchip, cal_info, core_id, pp_id, dp_id, DMPS_INVALID_VALUE_U8, SYS_AT_BR_CAL);
        /* 2.2 calender caculateion */
        CTC_ERROR_GOTO(_sys_at_datapath_calculate_general_calendar_parser(lchip, core_id, pp_id, dp_id, TRUE, cal, &walk_end, cal_info), 
            ret, RELEASE_PTR_RETURN_3);
        /* 2.3 config register */
        if(SYS_AT_MAX_CAL_LEN > walk_end)
        {
            CTC_ERROR_GOTO(_sys_at_datapath_bufretrv_calendar_write_to_register(lchip, core_id, pp_id, dp_id, cal, walk_end), 
                ret, RELEASE_PTR_RETURN_3);
        }
    }

    if (CHAN_DIR_IS_RX(dir_bmp))
    {
        /* 3.  set NetRx celender, do not consider CPUMAC */
        /* 3.1 info collect */
        _sys_at_calendar_speed_info_collect(lchip, cal_info, core_id, pp_id, dp_id, DMPS_INVALID_VALUE_U8, SYS_AT_NETRX_CAL);
        /* 3.2 calender caculateion */
        CTC_ERROR_GOTO(_sys_at_datapath_calculate_general_calendar_parser(lchip, core_id, pp_id, dp_id, FALSE, cal, &walk_end, cal_info), 
            ret, RELEASE_PTR_RETURN_3);
        /* 3.3 config register */
        if(SYS_AT_MAX_CAL_LEN > walk_end)
        {
            CTC_ERROR_GOTO(_sys_at_datapath_netrx_calendar_write_to_register(lchip, core_id, pp_id, dp_id, cal, walk_end), 
                ret, RELEASE_PTR_RETURN_3);
        }
    }

RELEASE_PTR_RETURN_3:
    mem_free(cal_info);
RELEASE_PTR_RETURN_2:
    mem_free(cal);
RELEASE_PTR_RETURN_1:
    return ret;
}

void
_sys_at_datapath_nettxx_calendar_1to2(uint32 *p_speed, uint16 *p_cal, uint16 p_walkend)
{
    uint32 cnt   = 0;
    uint32 num   = 0;
    uint32 step  = 0;
    uint32 index = 0;
    uint32 speed = 0;
    uint32 map[AT_NETTX_CAL_ENTRY_PRT_TXQM] = {0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15};

    for (cnt = 0; cnt < AT_NETTX_CAL_ENTRY_PRT_TXQM; cnt++)
    {
        p_cal[cnt] = AT_NETTX_CAL_INVAILD_VALUE;
    }

    for (cnt = 0; cnt < SYS_AT_MAC_CLIENT_PER_TXQM; cnt++)
    {
        speed = p_speed[cnt];
        num = speed / 50;
        if (0 != num)
        {
            step = (p_walkend + 1) / num;
            for (index = 0; index < num; index++)
            {
                p_cal[map[cnt] + index * step] = cnt;
            }
        }
    }

    return;
}

int32
_sys_at_datapath_nettx_common_calendar(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 dp_txqm_id,
                                        uint8 *p_error, uint16 *p_walk_end, uint16 *p_cal, sys_at_cal_info_collect_t* cal_info)
{
    int32  ret                  = CTC_E_NONE;
    uint8  txqm_client_id       = 0;
    uint16 dp_client_id         = 0;
    int16  cal_entry_num        = AT_NETTX_CAL_ENTRY_PRT_TXQM;
    uint32 speed                = 0;
    uint32 speed_org            = 0;
    uint32 speed_2nd            = 0;
    uint32 speed_2nd_sum        = 0;
    uint32 speed_2nd_violation  = 0;
    uint32 speed_2nd_sum_max    = 0;
    uint32 *speed_list          = NULL;
    uint32 *speed_list_2nd      = NULL;
    uint32 speed_max            = 0;
    uint16 core_pll             = 0;

    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"lchip %u, dp_id %u, dp_txqm_id %u\n", lchip, dp_id, dp_txqm_id);

    speed_list = (uint32*)mem_malloc(MEM_DMPS_MODULE, (SYS_AT_MAC_CLIENT_PER_TXQM + 1) * sizeof(uint32));
    if(NULL == speed_list)
    {
        return CTC_E_NO_MEMORY;
    }
    sal_memset(speed_list, 0, (SYS_AT_MAC_CLIENT_PER_TXQM + 1) * sizeof(uint32));

    speed_list_2nd = (uint32*)mem_malloc(MEM_DMPS_MODULE, SYS_AT_MAC_CLIENT_PER_TXQM * sizeof(uint32));
    if(NULL == speed_list_2nd)
    {
        mem_free(speed_list);
        return CTC_E_NO_MEMORY;
    }
    sal_memset(speed_list_2nd, 0, SYS_AT_MAC_CLIENT_PER_TXQM * sizeof(uint32));

    CTC_ERROR_GOTO(sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1), ret, RELEASE_PTR_RETURN);
    speed_max = (1350 == core_pll) ? SYS_AT_MAX_BANDWIDTH_PER_TXQM : (SYS_AT_MAX_BANDWIDTH_PER_TXQM / 2);

    if (SYS_AT_IS_1TO2_MAC_AGG_TXQM(lchip, pp_id, dp_id, dp_txqm_id))
    {
        for(txqm_client_id = 0; txqm_client_id < SYS_AT_MAC_CLIENT_PER_TXQM; txqm_client_id ++)
        {
            dp_client_id = dp_txqm_id * SYS_AT_MAC_CLIENT_PER_TXQM + txqm_client_id;
            speed        = cal_info[dp_client_id].speed;
            speed        = cal_info[dp_client_id].ock ? 
                             ((400 == speed) ? 425 :
                             (200 == speed) ? 215 :
                             (100 == speed) ? 110 :
                             (50  == speed) ? 55  : speed) : speed;
            speed        = (40 == speed) ? 50 : ((10 == speed) ? 25 : speed);
            speed_list[txqm_client_id] = speed * 10;
            speed_2nd_sum += speed;
        }

        if (speed_2nd_sum > speed_max)
        {
            speed_2nd_sum = 0;
            for(txqm_client_id = 0; txqm_client_id < SYS_AT_MAC_CLIENT_PER_TXQM; txqm_client_id ++)
            {
                dp_client_id = dp_txqm_id * SYS_AT_MAC_CLIENT_PER_TXQM + txqm_client_id;
                speed        = cal_info[dp_client_id].speed;
                speed        = (40 == speed) ? 50 : ((10 == speed) ? 25 : speed);
                speed_list[txqm_client_id] = speed * 10;
                speed_2nd_sum += speed;
            }
        }

        speed_list[SYS_AT_MAC_CLIENT_PER_TXQM] = (speed_max > speed_2nd_sum) ? ((speed_max - speed_2nd_sum) * 10) : 0;

        CTC_ERROR_GOTO(_sys_at_datapath_common_calendar(cal_entry_num, SYS_AT_MAC_CLIENT_PER_TXQM + 1, speed_list, 
                                                         p_error, p_walk_end, p_cal), ret, RELEASE_PTR_RETURN);
#if 0
        *p_walk_end = ((900 == core_pll) ? AT_NETTX_CAL_ENTRY_PRT_TXQM_LOW_CLK : AT_NETTX_CAL_ENTRY_PRT_TXQM) - 1;
        _sys_at_datapath_nettxx_calendar_1to2(speed_list, p_cal, *p_walk_end);
        *p_error = FALSE;
#endif
        goto RELEASE_PTR_RETURN;

    }

    for(txqm_client_id = 0; txqm_client_id < SYS_AT_MAC_CLIENT_PER_TXQM; txqm_client_id ++)
    {
        dp_client_id = dp_txqm_id * SYS_AT_MAC_CLIENT_PER_TXQM + txqm_client_id;
        speed_org = cal_info[dp_client_id].speed;

        speed = speed_org;
        speed_2nd = speed_org;

        //speed = (((speed_org > 0) && (speed_org < 1)) ? 1 : speed);
        speed_2nd = (((speed_org > 0) && (speed_org < 5)) ? 5 : speed_2nd);

        //speed_list[txqm_client_id] = ((2 == speed) ? 25 : (speed * 10));        /* 2.5G */
        speed_list[txqm_client_id]     = speed * 10;                 /* 2.5G */
        speed_list_2nd[txqm_client_id] = speed_2nd * 10;             /* x.5G */

        speed_2nd_sum += speed_list_2nd[txqm_client_id];
    }

    /* stage2 : violation detect (very important !!!!!! ) */
    speed_2nd_sum_max = 10 * SYS_AT_MAX_BANDWIDTH_PER_TXQM * core_pll / SYS_AT_CLK_DEFAULT;
    speed_2nd_violation = ((speed_2nd_sum > speed_2nd_sum_max) ? 1 : 0);

    /* stage3 : calculate calendar use common_calendar */
    if(speed_2nd_violation)
    {
        CTC_ERROR_GOTO(_sys_at_datapath_common_calendar(cal_entry_num, SYS_AT_MAC_CLIENT_PER_TXQM, speed_list, 
                                                         p_error, p_walk_end, p_cal), ret, RELEASE_PTR_RETURN);
    }
    else
    {
        CTC_ERROR_GOTO(_sys_at_datapath_common_calendar(cal_entry_num, SYS_AT_MAC_CLIENT_PER_TXQM, speed_list_2nd, 
                                                         p_error, p_walk_end, p_cal), ret, RELEASE_PTR_RETURN);
    }

    /* if TXQM is empty */
    if(0 == speed_2nd_sum)
    {
        *p_walk_end = 0;
    }
    
RELEASE_PTR_RETURN:
    mem_free(speed_list);
    mem_free(speed_list_2nd);

    return ret;
}

/*per-txqm operation*/
int32
_sys_at_datapath_calculate_nettx_calendar(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint32 dp_txqm_id, 
                                           uint16 *p_cal, uint16* walk_end, sys_at_cal_info_collect_t* cal_info)
{
    uint8  mactx_reorder_en[SYS_AT_MAC_CLIENT_PER_TXQM]    = {0};
    uint32 interval[SYS_AT_MAC_CLIENT_PER_TXQM]            = {0};/*interval,per port*/
    uint32 interval_cp[SYS_AT_MAC_CLIENT_PER_TXQM+1]       = {0};/*interval,per port*/
    uint32 interval_order[SYS_AT_MAC_CLIENT_PER_TXQM]      = {0};/*interval,per port*/
    uint8  active[SYS_AT_MAC_CLIENT_PER_TXQM+1]            = {0};/*active list*/
    uint8  en[SYS_AT_MAC_CLIENT_PER_TXQM]                  = {0};/*port enable*/
    uint8  first_cal_record_en[SYS_AT_MAC_CLIENT_PER_TXQM] = {0};/*record the index first select*/
    uint32 speed_sum        = 0;
    uint32 speed            = 0;
    uint32 oversub_bw       = 300;
    uint8  oversub_flag     = FALSE;
    uint32 member_num       = 0;
    uint32  bw_ratio        = 1000;
    /*uint8  spd_2nd_flag   = FALSE;*/
    /*uint8  spd_2nd_lock   = 0;*/
    uint8  spd_max_lock     = 0;
    uint8  low_prio         = FALSE;
    uint32 cycle            = 0;  /*calendar cycle*/
    uint8  done             = FALSE;
    uint8  error            = FALSE;
    uint8  force_sel        = FALSE;
    uint32 min_id           = 1;
    uint32 min_intv         = 10000;
    uint8  min_index        = 0;
    uint8  exchange_flag    = 0;
    uint32 selport          = 0;
    uint8  extra            = FALSE;
    uint8  active_flag      = FALSE;
    uint8  illegal          = FALSE;
    uint8  reload_active    = FALSE;
    uint8  mactx_illegal    = 0;
    uint8  txqm_client_id   = 0;
    uint8  i                = 0; 
    uint8  k                = 0;
    uint16 dp_client_id     = 0;
    uint32 actual_interval  = 0;
    uint32 expect_interval  = 0;
    uint32 multi_factor     = 1000;
    uint32 last_gap         = 0;
    uint32 interval_new     = 0;
    uint32 interval_sum     = 0;
    uint32 active_index_chg_dis = 0;
    uint32 intervalChk      = 0;
    uint32 intv_future      = 0;
    uint32 intv_future2     = 0;
    uint32 intv_margine     = 0;
    int32  ret = CTC_E_NONE;
    sys_at_nettx_cal_heap_t* p_heap = NULL;
    uint16 core_pll         = 0;

    (void) sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1);
   
    done = FALSE;
    error = FALSE;
    cycle = 0;
    speed_sum = 0;
    speed = 0;
    oversub_bw = 300;
    oversub_flag = FALSE;
    member_num = 0;
    bw_ratio = 1000;

    p_heap = (sys_at_nettx_cal_heap_t*)mem_malloc(MEM_DMPS_MODULE, sizeof(sys_at_nettx_cal_heap_t));
    CTC_ERROR_GOTO((NULL == p_heap) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_1);
    sal_memset(p_heap, 0, sizeof(sys_at_nettx_cal_heap_t));

    /*initial phase*/
    for(txqm_client_id = 0; txqm_client_id < SYS_AT_MAC_CLIENT_PER_TXQM; txqm_client_id++)
    {
        dp_client_id = dp_txqm_id * SYS_AT_MAC_CLIENT_PER_TXQM + txqm_client_id;
        speed = cal_info[dp_client_id].speed;
        speed_sum += speed;
        p_heap->first_cal_record[txqm_client_id] = 0;
        first_cal_record_en[txqm_client_id] = TRUE;
        p_heap->cnt_history[txqm_client_id] = 0;
    }

    if(speed_sum > oversub_bw)
    {
        oversub_flag = 1;
    }
    /*else 
    {
        bw_ratio = speed_sum * 1000 / 300;
    }*/

    /*look up low priority speed, inherit from Duet2*/
    /*spd_2nd_flag = FALSE;*/
    /*spd_2nd_lock = 0;*/
    spd_max_lock = 0;

    for(txqm_client_id = 0; txqm_client_id < SYS_AT_MAC_CLIENT_PER_TXQM; txqm_client_id++)
    {
        dp_client_id = dp_txqm_id * SYS_AT_MAC_CLIENT_PER_TXQM + txqm_client_id;
        speed = cal_info[dp_client_id].speed;
        if((1 <= speed) && (spd_max_lock < speed))
        {
            /*if((0 != spd_2nd_lock) && (spd_2nd_lock < spd_max_lock))
            {
                spd_2nd_flag = TRUE;
            }*/
            /*spd_2nd_lock = spd_max_lock;*/
            spd_max_lock = speed;
        }
    }
    for(txqm_client_id = 0; txqm_client_id < SYS_AT_MAC_CLIENT_PER_TXQM; txqm_client_id++)
    {
        dp_client_id = dp_txqm_id * SYS_AT_MAC_CLIENT_PER_TXQM + txqm_client_id;
        speed = cal_info[dp_client_id].speed;
        low_prio = oversub_flag && (spd_max_lock != speed);
        /*initial interval*/
        _sys_at_dp_calculate_interval(lchip, speed, 1, low_prio, 0, 1, bw_ratio, &interval_new, &(p_heap->cnt_history[txqm_client_id]));
        interval[txqm_client_id] = interval_new;
        /*initial active / enable and num*/
        if(1 <= speed)
        {
            active[txqm_client_id] = TRUE;
            en[txqm_client_id] = TRUE;
            p_heap->num[txqm_client_id] = 1;
            member_num++;
        }
        else  /*invalid port*/
        {
            active[txqm_client_id] = FALSE;
            en[txqm_client_id] = FALSE;
            p_heap->num[txqm_client_id] = 1;
            //member_num++;
        }
    }

    /*main function*/
    while((!done) && (!error))
    {
        /*reorder*/
        for(txqm_client_id = 1; txqm_client_id < SYS_AT_MAC_CLIENT_PER_TXQM+1; txqm_client_id++)
        {
            interval_cp[txqm_client_id] = interval[txqm_client_id-1];
        }
        /*stage1. bubble sort*/
        for(txqm_client_id = 1; txqm_client_id <= member_num; txqm_client_id++)
        {
            min_id = 1;
            min_intv = 10000;

            for(k = 1; k <= SYS_AT_MAC_CLIENT_PER_TXQM; k++)
            {
                if((interval_cp[k]) && (min_intv > interval_cp[k]))
                {
                    min_intv = interval_cp[k];
                    min_id = k;
                }
                else if((interval_cp[k]) && (min_intv == interval_cp[k]) && active[k])
                {
                    min_id = k;
                }
            }
            interval_cp[min_id] = 10000;
            interval_order[txqm_client_id] = min_intv;
            p_heap->portid_order[txqm_client_id] = min_id - 1;
        }

        /*stage2. calendar select*/
        min_index = p_heap->portid_order[1];  /*default min interval portid*/
        min_intv = interval_order[1];  /*default min interval*/

        /*interval violation deep check if reorder the minIndex*/
        active_index_chg_dis = 0;
        for(i = 1; i <= member_num; i++)
        {
            p_heap->expect_margine[i] = 1;
        }
        for(i = 1; i <= member_num; i++)
        {
            selport = p_heap->portid_order[i];

            dp_client_id = dp_txqm_id * SYS_AT_MAC_CLIENT_PER_TXQM + selport;
            speed = cal_info[dp_client_id].speed;
            
            interval_sum = p_heap->cnt_history[selport];
            _sys_at_dp_calculate_interval(lchip, speed, p_heap->num[selport], low_prio, extra, 0, bw_ratio, &intervalChk, &interval_sum);
            intv_future = interval_order[i] - 2 + intervalChk;
            intv_future2 = interval_order[i] - 2 + intervalChk * 2 - 1;

            if ( intv_future < member_num)
            {
                for ( k = intv_future; k <= member_num; k++)
                {
                    intv_margine = interval_order[k] - k;

                    if( intv_margine <= p_heap->expect_margine[k])
                    {
                        active_index_chg_dis = 1;
                    }

                    p_heap->expect_margine[k] ++;
                }
            }
            
            /*2nd*/
            /*means selPort will be a queue-jumper after reload interval*/
            if(intv_future2 < member_num)
            {
                for ( k = intv_future2; k <= member_num; k++)
                {
                    intv_margine = interval_order[k] - k;

                    if( intv_margine <= p_heap->expect_margine[k])
                    {
                        active_index_chg_dis = 1;
                    }

                    p_heap->expect_margine[k] ++;
                }
            }
        }
        
        /*add by zed to balance mac speed port bandwidth begin*/
        force_sel = 0;
        exchange_flag = 0;
        for (i = 1; i <= member_num; i++)
        {
            selport = p_heap->portid_order[i];

            dp_client_id = dp_txqm_id * SYS_AT_MAC_CLIENT_PER_TXQM + selport;
            speed = cal_info[dp_client_id].speed;

            /*
             * exchange minIndex due to : 
             * 1: not the fastest speed
             * 2: doesn't set exchange_flag before
             * 3: doesn't set force_sel before
             * 4: could't exchange active index
             */
            if((speed != spd_max_lock) 
                   && (!exchange_flag)
                   && (!force_sel)
                   && (active_index_chg_dis))
            {
                min_index = p_heap->portid_order[i];
                exchange_flag = 1;
                min_intv = interval_order[i];
            }

            if(i == interval_order[i])
            {
                force_sel = 1;
            }
        }
        
        /*detect error*/
        force_sel = FALSE;
        exchange_flag = FALSE;
        for(i = 1; i <= member_num; i++)
        {
            if(i > interval_order[i])
            {
                error = 2;
                SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, 
                    "%% [nettx]automatic constrain failed! failed id = %u, interval = %u, cycle = %u\n", 
                    i, interval_order[i], cycle);
                for(k = 1; k <= member_num; k++)
                {
                    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% [nettx]bubble sort index %u, interval %u\n", 
                        k, interval_order[k]) ;
                }
                break;
            } 
            /*get the mac id*/
            selport = p_heap->portid_order[i];
            /*exchange min_index due to : 
            1: must in active list 
            2: doesn't set exchange_flag before 
            3: doesn't set force_sel before 
            4: has small interval
            5: ~activeIndexChgDis*/
            if((active[selport]) && (!exchange_flag) && (!force_sel) && (!active_index_chg_dis))
            {
                min_index = p_heap->portid_order[i];
                exchange_flag = TRUE;
                min_intv = interval_order[i];
            }
            /*force_sel eq 1 means calendar can't select the portid_order index larger than i*/
            if(i == interval_order[i])
            {
                force_sel = TRUE;
            }
        }

        /*stage3. maintain DS*/
        /*stage3.1 all interval will decrease 1*/
        for(i = 0; i < SYS_AT_MAC_CLIENT_PER_TXQM; i++)
        {
            if(en[i])   
            {
                interval[i]--;
            }
        }
        /*stage3.2 generage calendar data*/
        p_cal[cycle] = min_index;

        /*stage3.3  re-calulate interval*/
        dp_client_id = dp_txqm_id * SYS_AT_MAC_CLIENT_PER_TXQM + min_index;
        speed = cal_info[dp_client_id].speed;
        extra = ((1 < min_intv) && force_sel);
        low_prio = oversub_flag && (!(spd_max_lock == speed));

        _sys_at_dp_calculate_interval(lchip, speed, p_heap->num[min_index], low_prio, extra, 1, bw_ratio, &interval_new, &(p_heap->cnt_history[min_index]));
        interval[min_index] = interval_new;
        p_heap->num[min_index]++;  /*num++ after re-calculate interval*/
        active[min_index] = FALSE;

        /*stage3.4 record the first calendar cycle*/
        if(first_cal_record_en[min_index])
        {
            p_heap->first_cal_record[min_index] = cycle;
            first_cal_record_en[min_index] = FALSE;
        }

        /*stage4. finish calendar calculate*/
        /*4.1 detect active flag*/
        active_flag = FALSE;
        for(txqm_client_id = 0; txqm_client_id < SYS_AT_MAC_CLIENT_PER_TXQM; txqm_client_id++)
        {
            if(active[txqm_client_id])
            {
                active_flag = TRUE;
            }
        }
        /*4.2 detect interval violation*/
        /*NetTx use 1*192+1 Byte to calculate interval average*/
        if(!active_flag)
        {
            illegal = FALSE;
            mactx_illegal = 0;
            /* mactx_has_violation in net tx */
            sal_memset(mactx_reorder_en, FALSE, SYS_AT_MAC_CLIENT_PER_TXQM*sizeof(uint8));
            for(txqm_client_id = 0; txqm_client_id < SYS_AT_MAC_CLIENT_PER_TXQM; txqm_client_id++)
            {
                dp_client_id = dp_txqm_id * SYS_AT_MAC_CLIENT_PER_TXQM + txqm_client_id;
                speed = cal_info[dp_client_id].speed;
                mactx_reorder_en[txqm_client_id] = FALSE;
                /*port enable*/
                if(0 != speed)
                {
                    /*192*1+1 B could reach performance*/
                    expect_interval = (SYS_AT_MAC_CALENDAR_BUS_WIDTH_TX+20+1)* core_pll * 8 / (speed*2);
                    actual_interval = ((cycle + 1) * multi_factor) / (p_heap->num[txqm_client_id] - 1);
                    if(actual_interval > expect_interval)
                    {
                        illegal = TRUE;
                        active[txqm_client_id] = TRUE;
                    }
                    /*tail --> head gap illegal calculate*/
                    last_gap = (p_heap->first_cal_record[txqm_client_id] > 2) ? (p_heap->first_cal_record[txqm_client_id] - 2) : 0;
                    last_gap = last_gap * bw_ratio / 1000;
                    /*last_gap = first_cal_record[i];*/
                    if(last_gap > interval[txqm_client_id])
                    {
                        illegal = TRUE;
                        active[txqm_client_id] = TRUE;
                    }
                }
            }
            /*special for MacTx*/
            /*adjust calendar if interval too small*/
            /*omitted*/
            /*becasue MacTx is abandoned, mactx_illegal is not funcational*/
            reload_active = (illegal || (0 != mactx_illegal));
            /*finish if no violation*/
            if(!reload_active)
            {
                done = TRUE;
                *walk_end = cycle;
            }
        }
        cycle++;
        if(AT_NETTX_CAL_ENTRY_PRT_TXQM < cycle)
        {
            error = 1;
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% [nettx]calendar cycle larger than 160, cycle %u \n", cycle);
        }
    }
    if(error)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% [nettx] NetTx calendar generate mistake ! error %u\n", error);
        ret = CTC_E_INVALID_PARAM;
        goto RELEASE_PTR_RETURN_2;
    }
    
RELEASE_PTR_RETURN_2:
    mem_free(p_heap);
RELEASE_PTR_RETURN_1:
    return ret;
}

int32
_sys_at_datapath_nettx_calendar_write_to_register(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id,
                                                    uint32 dp_txqm_id, uint16* p_cal, uint16 walk_end)
{
    uint8  i           = 0;
    uint32 val_32      = 0;
    uint32 cmd         = 0;
    uint32 index       = 0;
    uint32 is_back_cal = 0;
    uint32 tbl_id      = 0;
    uint32 fld_id      = 0;
    uint32 step        = 0;
    NetTxCal_m     nettx_cal;
    NetTxCalCtl_m  cal_ctl;
    NetTxMiscCtl_m misc_ctl;

    index = DRV_INS(0, 0);
    cmd   = DRV_IOR(NetTxMiscCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &misc_ctl));
    val_32   = GetNetTxMiscCtl(V, netTxReady_f, &misc_ctl);
    cmd      = DRV_IOR(NetTxCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &cal_ctl));
    step     = NetTxCalCtl_calEntry1Sel_f - NetTxCalCtl_calEntry0Sel_f;
    DRV_IOR_FIELD(lchip, NetTxCalCtl_t, (NetTxCalCtl_calEntry0Sel_f + step * dp_txqm_id), &is_back_cal, &cal_ctl);
    
    if(0 == val_32)
    {
        is_back_cal = 0;
    }
    else
    {
        is_back_cal = is_back_cal ? 0 : 1;
    }

    /* NetTxCal/NetTxCalBak-- txqm 0: 0~159 ; txqm 1: 160~319 ... */
    /* entry */ 
    tbl_id = is_back_cal ? NetTxCalBak_t : NetTxCal_t;
    fld_id = is_back_cal ? NetTxCalBak_calEntry_f : NetTxCal_calEntry_f;

    for(i = 0; i <= walk_end; i++)    
    {       
        index = DRV_INS(0, dp_txqm_id * AT_NETTX_CAL_ENTRY_PRT_TXQM + i);
        cmd   = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &nettx_cal));

        val_32   = (SYS_AT_MAC_CLIENT_PER_TXQM == p_cal[i]) ? AT_NETTX_CAL_INVAILD_VALUE : p_cal[i];
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, dp_txqm_id * AT_NETTX_CAL_ENTRY_PRT_TXQM + i, fld_id, &val_32, &nettx_cal);

        cmd      = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &nettx_cal));
    }

    /* WalkerEnd */
    index = DRV_INS(0, 0);
    cmd   = DRV_IOR(NetTxCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &cal_ctl));
    if(is_back_cal)
    {
        step   = NetTxCalCtl_walkerEnd1Bak_f - NetTxCalCtl_walkerEnd0Bak_f;
        fld_id = NetTxCalCtl_walkerEnd0Bak_f + step * dp_txqm_id;
    }
    else
    {
        step   = NetTxCalCtl_walkerEnd1_f - NetTxCalCtl_walkerEnd0_f;
        fld_id = NetTxCalCtl_walkerEnd0_f + step * dp_txqm_id;
    }    
    val_32   = walk_end;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetTxCalCtl_t, 0, 0, fld_id, &val_32, &cal_ctl);
    
    cmd      = DRV_IOW(NetTxCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &cal_ctl));

    /* bank sel */
    index = DRV_INS(0, 0);
    cmd   = DRV_IOR(NetTxCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &cal_ctl));

    val_32   = is_back_cal;
    step     = NetTxCalCtl_calEntry1Sel_f - NetTxCalCtl_calEntry0Sel_f;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, NetTxCalCtl_t, 0, 0,
        (NetTxCalCtl_calEntry0Sel_f + step * dp_txqm_id), &val_32, &cal_ctl);
    cmd      = DRV_IOW(NetTxCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &cal_ctl));

    return CTC_E_NONE;
}

void
_sys_at_datapath_update_nettx_calendar(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 dp_txqm_id, uint16 *p_cal, uint16* walk_end)
{
    uint16 cnt           = 0;
    uint16 quard_mac_num = 0;
    uint16 safe_num      = 0;
    uint16 walkend_txqm0 = 0;

    if((NULL == walk_end) || (NULL == p_cal))
    {
        return;
    }

    walkend_txqm0 = *walk_end;

    /* only txqm0 of DRV_CHIP_SUB_TYPE_3 should modify */
    if ((0 != dp_txqm_id) || (DRV_CHIP_SUB_TYPE_3 != SYS_AT_GET_CHIP_TYPE(lchip)))
    {
        return;
    }

    if ((0 == pp_id) || (3 == pp_id))
    {
        for (cnt = 0; cnt <= walkend_txqm0; cnt++)
        {
            if (p_cal[cnt] >= 8)
            {
                quard_mac_num++;
            }
        }
    }
    else if ((1 == pp_id) || (2 == pp_id))
    {
        for (cnt = 0; cnt <= walkend_txqm0; cnt++)
        {
            if (p_cal[cnt] < 8)
            {
                quard_mac_num++;
            }
        }
    }

    safe_num = quard_mac_num * 2;
    if (safe_num > (walkend_txqm0 + 1)) /* add invalid dp port id for MacAgg FIFO push */
    {
        for (cnt = walkend_txqm0 + 1; cnt < safe_num; cnt++)
        {
            p_cal[cnt] = 64;    /* invalid mac client */
        }

        SYS_USW_VALID_PTR_WRITE(walk_end, (safe_num - 1));
    }

    return;
}

int32
_sys_at_datapath_set_nettx_calendar(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 dp_txqm_id)
{
    int32   ret          = CTC_E_NONE;
    uint8   error        = TRUE;
    uint16  walk_end     = 0;
    uint16* cal          = NULL;
    sys_at_cal_info_collect_t* cal_info = NULL;

    cal_info = (sys_at_cal_info_collect_t*)mem_malloc(MEM_DMPS_MODULE,
        SYS_AT_CHAN_NUM_PER_PP * sizeof(sys_at_cal_info_collect_t));
    if(NULL == cal_info)
    {
        goto RELEASE_PTR_RETURN;
    }
    cal = (uint16*)mem_malloc(MEM_DMPS_MODULE, (SYS_AT_MAX_CAL_LEN * sizeof(uint16)));
    if(NULL == cal)
    {
        goto RELEASE_PTR_RETURN;
    }
    sal_memset(cal, 0, SYS_AT_MAX_CAL_LEN * sizeof(uint16));

    _sys_at_calendar_speed_info_collect(lchip, cal_info, core_id, pp_id, dp_id, dp_txqm_id, SYS_AT_NETTX_CAL);

    /*1. First Use new calendar algorithms*/
    CTC_ERROR_GOTO(_sys_at_datapath_nettx_common_calendar(lchip, core_id, pp_id, dp_id, dp_txqm_id, &error, &walk_end, cal, cal_info), 
                   ret, RELEASE_PTR_RETURN);
    /*2. If don't calculation, then use old calendar algorithms*/
    if(error)
    {
        sal_memset(cal, 0, SYS_AT_MAX_CAL_LEN * sizeof(uint16));
        walk_end = 0;
        CTC_ERROR_GOTO(_sys_at_datapath_calculate_nettx_calendar(lchip, core_id, pp_id, dp_id, dp_txqm_id, cal, &walk_end, cal_info), 
                       ret, RELEASE_PTR_RETURN);
    }

    /* Special config for M6_2 */
    //_sys_at_datapath_update_nettx_calendar(lchip, core_id, pp_id, dp_id, dp_txqm_id, cal, &walk_end);

    if(AT_NETTX_CAL_ENTRY_PRT_TXQM > walk_end)
    {
        CTC_ERROR_GOTO(_sys_at_datapath_nettx_calendar_write_to_register(lchip, core_id, pp_id, dp_id, dp_txqm_id, cal, walk_end), 
                       ret, RELEASE_PTR_RETURN);
    }

RELEASE_PTR_RETURN:
    mem_free(cal);
    mem_free(cal_info);
    
    return ret;
}

/*
 * @brief       used to configure all neccery tables 
 *              in BufRetrv moudle   
 */
int32
_sys_at_datapath_bufretrv_get_credit(uint8 lchip, uint32 speed, sys_datapath_bufsz_step_t *step, uint8 prio)
{  
    uint8  i = 0;
    uint16 core_pll = 0;
    const uint16 speed_num     = 8;
    const uint16 speed_lines[] = {0, 49, 50, 100, 200, 300, 400, 800};    // sizeof speed_lines must be speed_num
    const uint16 credits[][4]  = {   /*br_credit_local, br_credit_remote, sop buf, body buf, speed*/
                                     {0,                0,                0,       0 },    //MAX
                                     {8,                12,               40,      10},    //less than 50G
                                     {8,                12,               40,      10},    //50G
                                     {10,               15,               50,      12},    //100G
                                     {16,               20,               82,      16},    //200G
                                     {24,               30,               123,     24},    //300G
                                     {32,               40,               164,     32},    //400G
                                     {48,               72,               248,     64}};   //800G
    const uint16 credits_900[][4] = {   /*br_credit_local, br_credit_remote, sop buf, body buf, speed*/
                                     {0,                0,                0,       0 },    //MAX
                                     {11,               16,               52,      13},    //less than 50G
                                     {11,               16,               52,      13},    //50G
                                     {13,               20,               65,      16},    //100G
                                     {21,               26,               107,     21},    //200G
                                     {32,               39,               160,     32},    //300G
                                     {42,               52,               214,     42},    //400G
                                     {63,               94,               323,     84}};   //800G
    const uint16 prio_body_credit[8] = {0, 20, 20, 24, 32, 48, 64, 128};

    while((i < speed_num) && (speed > speed_lines[i]))
    {
        i++;
    }

    SYS_CONDITION_RETURN((i >= speed_num), CTC_E_INVALID_PARAM);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1));

    if (900 == core_pll)
    {
        step->br_credit_cfg        = credits_900[i][0];
        step->br_credit_cfg_remote = credits_900[i][1];
        step->sop_buf_num          = credits_900[i][2];
        step->body_buf_num         = prio ? prio_body_credit[i] : credits_900[i][3];
    }
    else
    {
        step->br_credit_cfg        = credits[i][0];
        step->br_credit_cfg_remote = credits[i][1];
        step->sop_buf_num          = credits[i][2];
        step->body_buf_num         = prio ? prio_body_credit[i] : credits[i][3];
    }

    return CTC_E_NONE;
}


/*
 * @brief       configure all nesessary credit tables
 * */
STATIC int32
_sys_at_datapath_set_bufretrv_credit(uint8 lchip, sys_dmps_db_chan_info_t* chan_info)
{
    uint8    core        = 0;
    uint8    core_id     = 0;
    uint8    pp_id       = 0;
    uint8    dp_id       = 0;
    uint8    speed_mode  = 0;
    uint8    prio        = 0;
    uint16   sub_chan_id = 0;
    uint32   cmd         = 0;
    uint32   tmp_val32   = 0;
    uint32   index       = 0;
    uint32   speed       = 0;
    PreBrChanBufThrd_m          buf_thrd;
    PostBrCreditConfigMem_m     body_sop_credit;
    sys_datapath_bufsz_step_t   step = {0};

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    CTC_PTR_VALID_CHECK(chan_info);
    core_id     = chan_info->core_id;
    pp_id       = chan_info->pp_id;
    dp_id       = chan_info->dp_id;
    speed_mode  = chan_info->speed_mode;
    prio        = chan_info->prio;
    sub_chan_id = chan_info->sub_chan_id;

    SYS_DATAPATH_SYS_MODE_TO_SPEED(speed_mode, speed);
    CTC_ERROR_RETURN(_sys_at_datapath_bufretrv_get_credit(lchip, speed, &step, prio));

    /* local core */
    core  = core_id;
    /* Buf Credit */
    index = DRV_INS(0, sub_chan_id);
    cmd   = DRV_IOR(PreBrChanBufThrd_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &buf_thrd));

    tmp_val32 = step.br_credit_cfg;
    DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrChanBufThrd_t, 0, sub_chan_id,
        PreBrChanBufThrd_bufThrd_f, &tmp_val32, &buf_thrd);

    cmd = DRV_IOW(PreBrChanBufThrd_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &buf_thrd));

    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        /* remote core */
        core  = (0 == core_id) ? 1 : 0;
        /* Buf Credit */
        index = DRV_INS(1, sub_chan_id);
        cmd   = DRV_IOR(PreBrChanBufThrd_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &buf_thrd));

        tmp_val32 = step.br_credit_cfg_remote;
        DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrChanBufThrd_t, 1, sub_chan_id,
            PreBrChanBufThrd_bufThrd_f, &tmp_val32, &buf_thrd);

        cmd = DRV_IOW(PreBrChanBufThrd_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &buf_thrd));
    }

    /* Body Credit */
    index = DRV_INS(0, sub_chan_id);
    cmd   = DRV_IOR(PostBrCreditConfigMem_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &body_sop_credit));

    tmp_val32 = step.sop_buf_num;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, PostBrCreditConfigMem_t, 0, sub_chan_id,
        PostBrCreditConfigMem_sopCreditCfg_f, &tmp_val32, &body_sop_credit);
    /* Sop Credit */
    tmp_val32 = step.body_buf_num;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, PostBrCreditConfigMem_t, 0, sub_chan_id,
        PostBrCreditConfigMem_bodyCreditCfg_f, &tmp_val32, &body_sop_credit);

    cmd = DRV_IOW(PostBrCreditConfigMem_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &body_sop_credit));

    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

/*Get virtual txqm id by dp_chan_id. 
Virtual txqm id is NOT mac txqm id. It is used for ASIC internal algorithms. 
Mac-Chan mapping will not influence virtual txqm id.
It divides channel id in one DP into 5 parts based on dp_chan_id (channel id 
in single DP  0~31) value range:

dp_chan_id      | vtxqm | vtxqm_chan
----------------+---------------
  0~ 15         | 0     | 0~15
 16~ 31         | 1     | 0~15
*/
int32
_sys_at_datapath_get_virtual_txqm_chan(uint8 dp_chan_id, uint8* p_vtxqm, uint8* p_vtxqm_chan)
{
    uint8 vtxqm       = 0;
    uint8 vtxqm_chan  = 0;

    SYS_CONDITION_RETURN((SYS_AT_CHAN_NUM_PER_DP <= dp_chan_id), CTC_E_INVALID_PARAM);

    vtxqm      = dp_chan_id / SYS_AT_CHAN_NUM_PER_TXQM;
    vtxqm_chan = dp_chan_id % SYS_AT_CHAN_NUM_PER_TXQM;

    SYS_USW_VALID_PTR_WRITE(p_vtxqm,      vtxqm);
    SYS_USW_VALID_PTR_WRITE(p_vtxqm_chan, vtxqm_chan);
    
    return CTC_E_NONE;
}

uint32
_sys_at_bufretrv_cal_divisors_for_WtCfgMem(uint16* weight_arr, uint16* divisors)
{
    uint8  dp_chan_id = 0;
    uint8  vtxqm      = 0;
    uint8  vtxqm_chan = 0;
    uint16 weight_of_txqms[SYS_AT_TXQM_NUM_PER_DP][SYS_AT_CHAN_NUM_PER_TXQM] = {{0}};  //index [virtual txqm id][chan id in single virtual txqm id]

    for(dp_chan_id = 0; dp_chan_id < SYS_AT_CHAN_NUM_PER_DP; dp_chan_id++)
    {
        _sys_at_datapath_get_virtual_txqm_chan(dp_chan_id, &vtxqm, &vtxqm_chan);
        weight_of_txqms[vtxqm][vtxqm_chan] = weight_arr[dp_chan_id];
    }

    for(vtxqm = 0; vtxqm < SYS_AT_TXQM_NUM_PER_DP; vtxqm++)
    {
        CTC_ERROR_RETURN(sys_usw_datapath_get_gcd((uint16*)(weight_of_txqms[vtxqm]), SYS_AT_CHAN_NUM_PER_TXQM,  &(divisors[vtxqm])));
    }

    return CTC_E_NONE;
}


/* @brief           set both EpeWfCfgMem and PkfWFCfgMem 
 * @weight_arr      origin weight, index by channel id 
 * @note            in @weight_arr, none-active channel value should be 0
 */
int32
_sys_at_datapath_bufretrv_write_weight_to_register(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint16* weight_arr)
{
    uint8  sub_chan_id    = 0;
    uint8  core           = 0;
    uint32 opt_weight     = 0;
    uint32 cmd            = 0;
    uint32 index          = 0;
    uint16 divisors       = 0;
    PostBrEpeWtCfgMem_m epe_weight_cfg;
    PreBrPktWtCfgMem_m pkt_weight_cfg;

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    //_sys_at_bufretrv_cal_divisors_for_WtCfgMem(weight_arr, divisors);
    CTC_ERROR_RETURN(sys_usw_datapath_get_gcd(weight_arr, SYS_AT_CHAN_NUM_PER_DP, &divisors));

    for(sub_chan_id = 0; sub_chan_id < SYS_AT_CHAN_NUM_PER_DP; sub_chan_id++)
    {
        index = DRV_INS(0, sub_chan_id);
        opt_weight = weight_arr[sub_chan_id] / divisors;
        opt_weight = (0 == opt_weight) ? 1 : opt_weight;

        /* PostBrEpeWtCfgMem */
        cmd = DRV_IOR(PostBrEpeWtCfgMem_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &epe_weight_cfg));

        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, PostBrEpeWtCfgMem_t, 0, sub_chan_id,
            PostBrEpeWtCfgMem_weight_f, &opt_weight, &epe_weight_cfg);

        cmd = DRV_IOW(PostBrEpeWtCfgMem_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &epe_weight_cfg));

        /* local core */
        core = core_id;
        /* PreBrPktWtCfgMem */
        index = DRV_INS(0, sub_chan_id);
        cmd = DRV_IOR(PreBrPktWtCfgMem_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pkt_weight_cfg));

        DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrPktWtCfgMem_t, 0, sub_chan_id,
            PreBrPktWtCfgMem_weight_f, &opt_weight, &pkt_weight_cfg);

        cmd = DRV_IOW(PreBrPktWtCfgMem_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pkt_weight_cfg));

        if (SYS_AT_CHIP_IS_DC(lchip))
        {
            /* remote core */
            core = (0 == core_id) ? 1 : 0;
            /* PreBrPktWtCfgMem */
            index = DRV_INS(1, sub_chan_id);
            cmd = DRV_IOR(PreBrPktWtCfgMem_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pkt_weight_cfg));

            DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrPktWtCfgMem_t, 1, sub_chan_id,
                PreBrPktWtCfgMem_weight_f, &opt_weight, &pkt_weight_cfg);

            cmd = DRV_IOW(PreBrPktWtCfgMem_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pkt_weight_cfg));
        }
    }

    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

int32
_sys_at_datapath_bufretrv_wrr_ctl_en(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 vtxqm, uint8 vchan, uint8 enable)
{
    uint8  core       = 0;
    uint32 index      = 0;
    uint32 cmd        = 0;
    uint32 val32      = 0;
    uint32 step       = 0;
    PostBrWrrCtl_m post_wrr_ctl;
    PreBrWrrCtl_m  pre_wrr_ctl;

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    /* local core */
    core  = core_id;
    index = DRV_INS(0, 0);

    cmd = DRV_IOR(PostBrWrrCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &post_wrr_ctl));

    cmd = DRV_IOR(PreBrWrrCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pre_wrr_ctl));

    step  = PostBrWrrCtl_txqm1ReqEn_f - PostBrWrrCtl_txqm0ReqEn_f;
    DRV_IOR_FIELD(lchip, PostBrWrrCtl_t, (PostBrWrrCtl_txqm0ReqEn_f + step * vtxqm), &val32, &post_wrr_ctl);
    if (enable)
    {
        CTC_BIT_SET(val32, vchan);
    }
    else
    {
        CTC_BIT_UNSET(val32, vchan);
    }
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, PostBrWrrCtl_t, 0, 0,
        (PostBrWrrCtl_txqm0ReqEn_f + step * vtxqm), &val32, &post_wrr_ctl);

    step  = PreBrWrrCtl_txqm1ReqEn_f - PreBrWrrCtl_txqm0ReqEn_f;
    DRV_IOR_FIELD(lchip, PreBrWrrCtl_t, (PreBrWrrCtl_txqm0ReqEn_f + step * vtxqm), &val32, &pre_wrr_ctl);
    if (enable)
    {
        CTC_BIT_SET(val32, vchan);
    }
    else
    {
        CTC_BIT_UNSET(val32, vchan);
    }
    DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrWrrCtl_t, 0, 0,
        (PreBrWrrCtl_txqm0ReqEn_f + step * vtxqm), &val32, &pre_wrr_ctl);

    cmd = DRV_IOW(PostBrWrrCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &post_wrr_ctl));

    cmd = DRV_IOW(PreBrWrrCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pre_wrr_ctl));

    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        /* remote core */
        core  = (0 == core_id) ? 1 : 0;
        index = DRV_INS(1, 0);

        cmd = DRV_IOR(PreBrWrrCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pre_wrr_ctl));

        step  = PreBrWrrCtl_txqm1ReqEn_f - PreBrWrrCtl_txqm0ReqEn_f;
        DRV_IOR_FIELD(lchip, PreBrWrrCtl_t, (PreBrWrrCtl_txqm0ReqEn_f + step * vtxqm), &val32, &pre_wrr_ctl);
        if (enable)
        {
            CTC_BIT_SET(val32, vchan);
        }
        else
        {
            CTC_BIT_UNSET(val32, vchan);
        }
        DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrWrrCtl_t, 1, 0,
            (PreBrWrrCtl_txqm0ReqEn_f + step * vtxqm), &val32, &pre_wrr_ctl);

        cmd = DRV_IOW(PreBrWrrCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pre_wrr_ctl));
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_bufretrv_wrr_ctl(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint16 weight_sum[2])
{
    uint8  dp_txqm_id = 0;
    uint8  core       = 0;
    uint16 divisor    = 0;
    uint32 step       = 0;
    uint32 index      = 0;
    uint32 cmd        = 0;
    uint32 opt_weight = 0;
    PostBrWrrCtl_m post_wrr_ctl;
    PreBrWrrCtl_m  pre_wrr_ctl;

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    /* local core */
    core  = core_id;
    index = DRV_INS(0, 0);
    CTC_ERROR_RETURN(sys_usw_datapath_get_gcd(weight_sum, 2, &divisor));

    cmd = DRV_IOR(PostBrWrrCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &post_wrr_ctl));

    cmd = DRV_IOR(PreBrWrrCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pre_wrr_ctl));

    for(dp_txqm_id = 0; dp_txqm_id < SYS_AT_TXQM_NUM_PER_DP; dp_txqm_id++)
    {
        opt_weight = weight_sum[dp_txqm_id] / divisor;
        opt_weight = (0 == opt_weight) ? 1 : opt_weight;
        step       = PostBrWrrCtl_txqm1WtCfg_f - PostBrWrrCtl_txqm0WtCfg_f;
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, PostBrWrrCtl_t, 0, 0,
            (PostBrWrrCtl_txqm0WtCfg_f + step * dp_txqm_id), &opt_weight, &post_wrr_ctl);

        step       = PreBrWrrCtl_txqm1WtCfg_f - PreBrWrrCtl_txqm0WtCfg_f;
        DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrWrrCtl_t, 0, 0,
            (PreBrWrrCtl_txqm0WtCfg_f + step * dp_txqm_id), &opt_weight, &pre_wrr_ctl);
    }

    cmd = DRV_IOW(PostBrWrrCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &post_wrr_ctl));

    cmd = DRV_IOW(PreBrWrrCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pre_wrr_ctl));

    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        /* remote core */
        core  = (0 == core_id) ? 1 : 0;
        index = DRV_INS(1, 0);
        CTC_ERROR_RETURN(sys_usw_datapath_get_gcd(weight_sum, 2, &divisor));

        cmd = DRV_IOR(PreBrWrrCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pre_wrr_ctl));

        for(dp_txqm_id = 0; dp_txqm_id < SYS_AT_TXQM_NUM_PER_DP; dp_txqm_id++)
        {
            opt_weight = weight_sum[dp_txqm_id] / divisor;
            opt_weight = (0 == opt_weight) ? 1 : opt_weight;

            step       = PreBrWrrCtl_txqm1WtCfg_f - PreBrWrrCtl_txqm0WtCfg_f;
            DRV_IOW_ENTRY_NZ(core, pp_id, dp_id, lchip, PreBrWrrCtl_t, 1, 0,
                (PreBrWrrCtl_txqm0WtCfg_f + step * dp_txqm_id), &opt_weight, &pre_wrr_ctl);
        }

        cmd = DRV_IOW(PreBrWrrCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core, pp_id, dp_id, cmd, &pre_wrr_ctl));
    }

    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

STATIC int32
_sys_at_datapath_set_bufretrv_wrr_weight(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint8  vtxqm         = 0;
    uint8  vtxqm_chan    = 0;
    uint8  sub_chan_id   = 0;
    uint8  chan_idx      = 0;
    uint8  speed_mode    = 0;
    uint16 chan_id       = 0;
    uint16 wrrbase       = 0;
    uint16 weight_sum[2] = {0};    /* DP txqm:0 1 */
    uint16 chan_list[SYS_AT_CHAN_NUM_PER_DP]  = {0};
    uint16 weight_arr[SYS_AT_CHAN_NUM_PER_DP] = {0};
    sys_dmps_db_upt_info_t port_info          = {0};

    CTC_ERROR_RETURN(_sys_at_datapath_get_dp_chan(lchip, core_id, pp_id, dp_id, chan_list, CHAN_DIR_TX));

    for (chan_idx = 0; chan_idx < SYS_AT_CHAN_NUM_PER_DP; chan_idx++)
    {
        chan_id = chan_list[chan_idx];
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id));

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID,               chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SUB_CHAN_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SPEED_MODE);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID, sub_chan_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE,  speed_mode);

        SYS_DATAPATH_SYS_SPEED_TO_WRRCFG(speed_mode, wrrbase);

        CTC_ERROR_RETURN(_sys_at_datapath_get_virtual_txqm_chan(sub_chan_id, &vtxqm, &vtxqm_chan));

        CTC_ERROR_RETURN(_sys_at_datapath_bufretrv_wrr_ctl_en(lchip, core_id, pp_id, dp_id, vtxqm, vtxqm_chan, 1));

        weight_sum[vtxqm]      += wrrbase;
        weight_arr[sub_chan_id] = wrrbase;
    }

    /*write tables*/
    CTC_ERROR_RETURN(_sys_at_datapath_bufretrv_write_weight_to_register(lchip, core_id, pp_id, dp_id, weight_arr));
    /*txqm0..1ReqEn*/
    CTC_ERROR_RETURN(_sys_at_datapath_bufretrv_wrr_ctl(lchip, core_id, pp_id, dp_id, weight_sum));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_bufretrv_init(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint8  chan_idx   = 0;
    uint16 chan_id    = 0;
    uint16 chan_list[SYS_AT_CHAN_NUM_PER_DP]  = {0};
    sys_dmps_db_chan_info_t chan_info         = {0};

    CTC_ERROR_RETURN(_sys_at_datapath_get_dp_chan(lchip, core_id, pp_id, dp_id, chan_list, CHAN_DIR_TX));
    for (chan_idx = 0; chan_idx < SYS_AT_CHAN_NUM_PER_DP; chan_idx++)
    {
        chan_id = chan_list[chan_idx];
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id));

        chan_info.chan_id = chan_id;
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, &chan_info, CHAN_DIR_TX));

        CTC_ERROR_RETURN(_sys_at_datapath_set_bufretrv_credit(lchip, &chan_info));

        CTC_ERROR_RETURN(_sys_at_datapath_set_br_mode(lchip, &chan_info));
        CTC_ERROR_RETURN(_sys_at_datapath_set_bs_mode(lchip, &chan_info));
    }

    CTC_ERROR_RETURN(_sys_at_datapath_set_bufretrv_wrr_weight(lchip, core_id, pp_id, dp_id));

    return CTC_E_NONE;
}

int32
 _sys_at_datapath_epe_speed_to_credit(uint16 speed)
{
    uint16 i = 0;
    const uint16 line_num = 10;
                              /*<    10, 10, 25, 40, 50, 100, 200, 400, 800*/
    const uint16 speed_lines[] = {0,  1, 10, 25, 40, 50, 100, 200, 400, 800};
    const uint32 credits[]     = {0, 15, 15, 15, 15, 15,  20,  26,  52, 80};
    
    while((i < line_num) && (speed > speed_lines[i]))
    {
        i++;
    }
    SYS_CONDITION_RETURN((i >= line_num), 0);

    return credits[i];
}

 int32
 _sys_at_datapath_epe_xsec_speed_to_credit(uint16 speed)
{
    uint16 i = 0;
    const uint16 line_num = 10;
                              /*<    10, 10, 25, 40, 50, 100, 200, 400, 800*/
    const uint16 speed_lines[] = {0,  1, 10, 25, 40, 50, 100, 200, 400, 800};
    const uint32 credits[]     = {0,  4,  4,  8,  8, 16,  32,  64, 128, 128};
    
    while((i < line_num) && (speed > speed_lines[i]))
    {
        i++;
    }
    SYS_CONDITION_RETURN((i >= line_num), 0);

    return credits[i];
}

int32
_sys_at_datapath_epe_xg_lg_enable(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint8  dp_txqm_id     = 0;
    uint8  port_type      = 0;
    uint16 start_chan     = 0;
    uint16 end_chan       = 0;
    uint16 speed          = 0;
    uint16 chan_id        = 0;
    uint32 cmd            = 0;
    uint32 index          = 0;
    uint32 txqm_client_id = 0;
    uint32 xg_bitmap[2]   = {0};     /* 2 txqm */
    uint32 xlg_bitmap[2]  = {0};
    uint8  step           = EpeSchedulePortEnableCfg_cfgGroup1LSPortEn_f - EpeSchedulePortEnableCfg_cfgGroup0LSPortEn_f;
    sys_dmps_db_chan_info_t chan_info = {0};
    sys_dmps_db_upt_info_t port_info  = {0};
    EpeSchedulePortEnableCfg_m port_en_cfg;

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    start_chan = core_id * AT_NW_CHAN_NUM_PER_CORE + pp_id * SYS_AT_NW_CHAN_NUM_PER_PP + dp_id * SYS_AT_NW_CHAN_NUM_PER_DP;
    end_chan   = start_chan + SYS_AT_NW_CHAN_NUM_PER_DP;

    chan_info.core_id = core_id;
    chan_info.pp_id   = pp_id;
    chan_info.dp_id   = dp_id;

    /*network chan */
    for (chan_id = start_chan; chan_id < end_chan; chan_id++)
    {
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id));

        chan_info.chan_id = chan_id;
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_TXQM_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SUB_CHAN_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SPEED_MODE);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_TXQM_ID,       chan_info.txqm_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID,   chan_info.sub_chan_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID, chan_info.mac_client_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE,    chan_info.speed_mode);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,          port_type);
        SYS_CONDITION_CONTINUE(SYS_DMPS_NETWORK_PORT != port_type);

        SYS_DATAPATH_SYS_MODE_TO_SPEED(chan_info.speed_mode, speed);

        dp_txqm_id     = chan_info.txqm_id;
        txqm_client_id = chan_info.mac_client_id % SYS_AT_MAC_CLIENT_PER_TXQM;

        if(speed < 100)
        {
            CTC_BMP_SET(&xg_bitmap[dp_txqm_id], txqm_client_id);
            CTC_BMP_UNSET(&xlg_bitmap[dp_txqm_id], txqm_client_id);
        }
        else
        {
            CTC_BMP_UNSET(&xg_bitmap[dp_txqm_id], txqm_client_id);
            CTC_BMP_SET(&xlg_bitmap[dp_txqm_id], txqm_client_id);
        }
    }

    index = DRV_INS(0, 0);
    cmd   = DRV_IOR(EpeSchedulePortEnableCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &port_en_cfg));

    for(dp_txqm_id = 0; dp_txqm_id < SYS_AT_TXQM_NUM_PER_DP; dp_txqm_id++)
    {
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, EpeSchedulePortEnableCfg_t, 0, 0,
            (EpeSchedulePortEnableCfg_cfgGroup0LSPortEn_f + dp_txqm_id * step), &xg_bitmap[dp_txqm_id], &port_en_cfg);
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, EpeSchedulePortEnableCfg_t, 0, 0,
            (EpeSchedulePortEnableCfg_cfgGroup0HSPortEn_f + dp_txqm_id * step), &xlg_bitmap[dp_txqm_id], &port_en_cfg);
    }

    cmd = DRV_IOW(EpeSchedulePortEnableCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &port_en_cfg));

    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_epe_credit(uint8 lchip, sys_dmps_db_chan_info_t* chan_info)
{
    uint8   core_id        = 0;
    uint8   pp_id          = 0;
    uint8   dp_id          = 0;
    uint8   dp_client_id   = 0;
    uint32  index          = 0;
    uint32  cmd            = 0;
    uint32  credit         = 0;
    uint16  speed          = 0;
    uint32  tbl_id         = EpeScheduleToNetTxPortCreditCtl_t;
    uint32  fld_id         = 0;
    uint32  step           = EpeScheduleToNetTxPortCreditCtl_cfgNetTxPort1CreditThrd_f -
                                EpeScheduleToNetTxPortCreditCtl_cfgNetTxPort0CreditThrd_f;
    EpeScheduleToNetTxPortCreditCtl_m epe_credit  = {{0}};
    EpeScheduleNetPortXSecCreditCtl_m epe_xsec_credit;

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    CTC_PTR_VALID_CHECK(chan_info);
    core_id      = chan_info->core_id;
    pp_id        = chan_info->pp_id;
    dp_id        = chan_info->dp_id;
    dp_client_id = chan_info->mac_client_id;

    SYS_DATAPATH_SYS_MODE_TO_SPEED(chan_info->speed_mode, speed);
    credit = _sys_at_datapath_epe_speed_to_credit(speed);

    index  = DRV_INS(0, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &epe_credit));

    fld_id = EpeScheduleToNetTxPortCreditCtl_cfgNetTxPort0CreditThrd_f + dp_client_id * step;

    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, 0, fld_id, &credit, &epe_credit);
    
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &epe_credit));

    credit = _sys_at_datapath_epe_xsec_speed_to_credit(speed);
    tbl_id = EpeScheduleNetPortXSecCreditCtl_t;
    index  = DRV_INS(0, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &epe_xsec_credit));

    fld_id = EpeScheduleNetPortXSecCreditCtl_cfgPort0XSecCreditThrd_f + dp_client_id * step;

    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, 0, fld_id, &credit, &epe_xsec_credit);
    
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &epe_xsec_credit));

    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

int32
_sys_at_epe_get_net_info(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id,
                            uint16 low_weight_sum[SYS_AT_TXQM_NUM_PER_DP],
                            uint16 high_weight_sum[SYS_AT_TXQM_NUM_PER_DP], 
                            uint16 weight_arr[SYS_AT_TXQM_NUM_PER_DP][SYS_AT_MAC_CLIENT_PER_TXQM],
                            uint16 all_weights[3])
{
    uint8  txqm_client_id = 0;
    uint8  dp_txqm_id     = 0;
    uint8  chan_idx       = 0;
    uint8  port_type      = 0;
    uint16 weight         = 0;
    uint16 speed          = 0;
    uint16 chan_id        = 0;
    uint16 chan_list[SYS_AT_CHAN_NUM_PER_DP]  = {0};
    sys_dmps_db_chan_info_t chan_info         = {0};
    sys_dmps_db_upt_info_t port_info          = {0};
    
    CTC_ERROR_RETURN(_sys_at_datapath_get_dp_chan(lchip, core_id, pp_id, dp_id, chan_list, CHAN_DIR_TX));

    chan_info.core_id = core_id;
    chan_info.pp_id   = pp_id;
    chan_info.dp_id   = dp_id;

    for (chan_idx = 0; chan_idx < SYS_AT_CHAN_NUM_PER_DP; chan_idx++)
    {
        chan_id = chan_list[chan_idx];
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id));

        chan_info.chan_id = chan_id;
        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_TXQM_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SUB_CHAN_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SPEED_MODE);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_TXQM_ID,       chan_info.txqm_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID,   chan_info.sub_chan_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID, chan_info.mac_client_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE,    chan_info.speed_mode);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,          port_type);

        SYS_DATAPATH_SYS_MODE_TO_SPEED(chan_info.speed_mode, speed);
        SYS_DATAPATH_SYS_SPEED_TO_WRRCFG(chan_info.speed_mode, weight);

        if (SYS_DMPS_NETWORK_PORT == port_type)
        {
            dp_txqm_id     = chan_info.txqm_id;
            txqm_client_id = chan_info.mac_client_id % SYS_AT_MAC_CLIENT_PER_TXQM;

            if(speed < 100)
            {
                weight_arr[dp_txqm_id][txqm_client_id] = weight;
                low_weight_sum[dp_txqm_id]          += weight;
            }
            else
            {
                weight_arr[dp_txqm_id][txqm_client_id] = weight;
                high_weight_sum[dp_txqm_id]         += weight;
            }

            all_weights[0] += weight;
        }
        else if (SYS_AT_IS_MISC_PORT(port_type))
        {
            all_weights[1] += weight;
        }
        else if (SYS_AT_IS_LOOP_PORT(port_type))
        {
            all_weights[2] += weight;
        }
    }

    return CTC_E_NONE;
}

int32 
_sys_at_epe_write_net_chan_weight_cfg(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, 
                                        uint16 net_weights[SYS_AT_TXQM_NUM_PER_DP][SYS_AT_MAC_CLIENT_PER_TXQM])
{
    uint8  dp_txqm_id     = 0;
    uint16 dp_client_id   = 0;
    uint16 txqm_client_id = 0;
    uint32 tbl_id         = 0;
    uint32 index          = 0;
    uint32 cmd            = 0;
    uint32 opt_weight     = 0;
    uint16 divisor        = 0;
    uint32 step           = 0;
    EpeScheduleNetPortWeightConfig_m net_port_weight_cfg;

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    for(dp_txqm_id = 0; dp_txqm_id < SYS_AT_TXQM_NUM_PER_DP; dp_txqm_id++)
    {
        CTC_ERROR_RETURN(sys_usw_datapath_get_gcd(net_weights[dp_txqm_id], SYS_AT_MAC_CLIENT_PER_TXQM, &divisor));
        for(txqm_client_id = 0; txqm_client_id < SYS_AT_MAC_CLIENT_PER_TXQM; txqm_client_id++)
        {
            //SYS_CONDITION_CONTINUE(0 == net_weights[dp_txqm_id][txqm_client_id]);
            
            dp_client_id = dp_txqm_id * SYS_AT_MAC_CLIENT_PER_TXQM + txqm_client_id;
            index = DRV_INS(0, 0);

            tbl_id = EpeScheduleNetPortWeightConfig_t;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &net_port_weight_cfg));
 
            opt_weight = net_weights[dp_txqm_id][txqm_client_id] / divisor;
            opt_weight = (0 == opt_weight) ? 1 : opt_weight;
            step       = EpeScheduleNetPortWeightConfig_cfgNetPort1Weight_f -
                            EpeScheduleNetPortWeightConfig_cfgNetPort0Weight_f;
            DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, 0,
                (EpeScheduleNetPortWeightConfig_cfgNetPort0Weight_f + step * dp_client_id), &opt_weight, &net_port_weight_cfg);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &net_port_weight_cfg));
        }
    }

    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

int32
_sys_at_epe_write_wrr_weight_cfg(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id,
                                uint16 low_weight_sum[SYS_AT_TXQM_NUM_PER_DP], 
                                uint16 high_weight_sum[SYS_AT_TXQM_NUM_PER_DP],
                                uint16  all_weights[3])
{
    uint8  dp_txqm_id     = 0;
    uint8  step           = 0;
    uint16 divisor_hl     = 0;
    uint16 divisor        = 0;
    uint32 opt_weight     = 0;
    uint32 index          = 0;
    uint32 cmd            = 0;
    uint16 high_low[SYS_AT_TXQM_NUM_PER_DP][2] = {{0}};  //index: [dp_txqm_id][0 or 1, high weight sum or low weight sum]
    uint16 txqm_weight[SYS_AT_TXQM_NUM_PER_DP] = {0};    //high + low in every txqm    index: [dp_txqm_id]
    EpeScheduleWrrWeightConfig_m wrr_cfg;

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    /*info collection*/
    for (dp_txqm_id = 0; dp_txqm_id < SYS_AT_TXQM_NUM_PER_DP; dp_txqm_id++)
    {
        high_low[dp_txqm_id][0] = high_weight_sum[dp_txqm_id];
        high_low[dp_txqm_id][1] = low_weight_sum[dp_txqm_id];
        txqm_weight[dp_txqm_id] = high_weight_sum[dp_txqm_id] + low_weight_sum[dp_txqm_id];
    }
    CTC_ERROR_RETURN(sys_usw_datapath_get_gcd(txqm_weight, SYS_AT_TXQM_NUM_PER_DP, &divisor));

    index = DRV_INS(0, 0);
    cmd = DRV_IOR(EpeScheduleWrrWeightConfig_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &wrr_cfg));

    /*network port*/
    for (dp_txqm_id = 0; dp_txqm_id < SYS_AT_TXQM_NUM_PER_DP; dp_txqm_id++)
    {        
        /*LS & HS*/
        CTC_ERROR_RETURN(sys_usw_datapath_get_gcd(high_low[dp_txqm_id], 2, &divisor_hl));
        
        step = EpeScheduleWrrWeightConfig_toGroup1LsWtCfg_f - EpeScheduleWrrWeightConfig_toGroup0LsWtCfg_f;
        opt_weight = low_weight_sum[dp_txqm_id] / divisor_hl;
        opt_weight = (0 == opt_weight) ? 1 : opt_weight;
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, EpeScheduleWrrWeightConfig_t, 0, 0,
            (EpeScheduleWrrWeightConfig_toGroup0LsWtCfg_f + dp_txqm_id * step), &opt_weight, &wrr_cfg);

        step = EpeScheduleWrrWeightConfig_toGroup1HsWtCfg_f - EpeScheduleWrrWeightConfig_toGroup0HsWtCfg_f;
        opt_weight = high_weight_sum[dp_txqm_id] / divisor_hl;
        opt_weight = (0 == opt_weight) ? 1 : opt_weight;
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, EpeScheduleWrrWeightConfig_t, 0, 0,
            (EpeScheduleWrrWeightConfig_toGroup0HsWtCfg_f + dp_txqm_id * step), &opt_weight, &wrr_cfg);

        /*general*/
        step = EpeScheduleWrrWeightConfig_cfgGroup5Txqm1WtCfg_f - EpeScheduleWrrWeightConfig_cfgGroup5Txqm0WtCfg_f;
        opt_weight = txqm_weight[dp_txqm_id] / divisor;
        opt_weight = (0 == opt_weight) ? 1 : opt_weight;
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, EpeScheduleWrrWeightConfig_t, 0, 0,
            (EpeScheduleWrrWeightConfig_cfgGroup5Txqm0WtCfg_f + dp_txqm_id * step), &opt_weight, &wrr_cfg);
    }

    /* NetWork:Misc:Loop */
    CTC_ERROR_RETURN(sys_usw_datapath_get_gcd(all_weights, 3, &divisor));
    opt_weight = all_weights[0] / divisor;
    opt_weight = (0 == opt_weight) ? 1 : opt_weight;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, EpeScheduleWrrWeightConfig_t, 0, 0,
            EpeScheduleWrrWeightConfig_cfgGroup7NetWtCfg_f, &opt_weight, &wrr_cfg);

    opt_weight = all_weights[1] / divisor;
    opt_weight = (0 == opt_weight) ? 1 : opt_weight;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, EpeScheduleWrrWeightConfig_t, 0, 0,
            EpeScheduleWrrWeightConfig_cfgGroup7MiscWtCfg_f, &opt_weight, &wrr_cfg);

    opt_weight = all_weights[2] / divisor;
    opt_weight = (0 == opt_weight) ? 1 : opt_weight;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, EpeScheduleWrrWeightConfig_t, 0, 0,
            EpeScheduleWrrWeightConfig_cfgGroup7LoopWtCfg_f, &opt_weight, &wrr_cfg);

    cmd = DRV_IOW(EpeScheduleWrrWeightConfig_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &wrr_cfg));

    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_epe_wrr_weight(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint16  low_weight_sum[SYS_AT_TXQM_NUM_PER_DP]  = {0};   //index: dp_txqm_id 0~1
    uint16  high_weight_sum[SYS_AT_TXQM_NUM_PER_DP] = {0};   //index: dp_txqm_id 0~1
    /*index: [dp_txqm_id 0~1][txqm_mac_id 0~15]*/
    uint16  net_weights[SYS_AT_TXQM_NUM_PER_DP][SYS_AT_MAC_CLIENT_PER_TXQM] = {{0}};
    uint16  all_weights[3] = {0}; /* 0: network, 1: misc, 2: loop */

    /*get info*/
    CTC_ERROR_RETURN(_sys_at_epe_get_net_info(lchip, core_id, pp_id, dp_id,
        low_weight_sum, high_weight_sum, net_weights, all_weights));
    /*config network port epe weight*/
    CTC_ERROR_RETURN(_sys_at_epe_write_net_chan_weight_cfg(lchip, core_id, pp_id, dp_id, net_weights));
    /*config wrr ls & hs weight*/ 
    CTC_ERROR_RETURN(_sys_at_epe_write_wrr_weight_cfg(lchip, core_id, pp_id, dp_id,
        low_weight_sum, high_weight_sum, all_weights));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_epe_misc_port_id_cfg(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint32  index      = 0;
    uint32  cmd        = 0;
    uint32  value      = 0;
    EpeSchedulePortIdCfg_m epe_port;

    index = DRV_INS(0, 0);
    cmd = DRV_IOR(EpeSchedulePortIdCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &epe_port));
    value = 0x20; //misc port: 32
    DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, EpeSchedulePortIdCfg_t, 0,
        EpeSchedulePortIdCfg_cfgMiscPortId_f, &value, &epe_port);

    cmd = DRV_IOW(EpeSchedulePortIdCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &epe_port));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_epe_extra_cfg(uint8 lchip,uint8 core_id)
{
    uint32  index      = 0;
    uint32  cmd        = 0;
    uint32  value      = 0;
    EpeHdrEditExtraCreditConfig_m epe_ext;

    /*write EpeHdrEditExtraCreditConfig.extraCreditUplink 2 to solve stacking port queue blocked*/
    cmd = DRV_IOR(EpeHdrEditExtraCreditConfig_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &epe_ext));
    value = 2;
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, EpeHdrEditExtraCreditConfig_t, 0,
        EpeHdrEditExtraCreditConfig_extraCreditUplink_f, &value, &epe_ext);
    cmd = DRV_IOW(EpeHdrEditExtraCreditConfig_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &epe_ext));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_epe_init(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint8  port_type  = 0;
    uint16 chan_id    = 0;
    uint16 start_chan = 0;
    uint16 end_chan   = 0;
    sys_dmps_db_chan_info_t chan_info = {0};
    sys_dmps_db_upt_info_t port_info  = {0};

    start_chan = core_id * AT_NW_CHAN_NUM_PER_CORE + pp_id * SYS_AT_NW_CHAN_NUM_PER_PP + dp_id * SYS_AT_NW_CHAN_NUM_PER_DP;
    end_chan   = start_chan + SYS_AT_NW_CHAN_NUM_PER_DP;

    chan_info.chan_id = chan_id;
    chan_info.core_id = core_id;
    chan_info.pp_id   = pp_id;
    chan_info.dp_id   = dp_id;
    
    for (chan_id = start_chan; chan_id < end_chan; chan_id++)
    {
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id));

        CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
        DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SUB_CHAN_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SPEED_MODE);
        DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID,   chan_info.sub_chan_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID, chan_info.mac_client_id);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SPEED_MODE,    chan_info.speed_mode);
        DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,          port_type);

        if(SYS_DMPS_NETWORK_PORT == port_type)
        {
            CTC_ERROR_RETURN(_sys_at_datapath_set_epe_credit(lchip, &chan_info));
        }
    }

    CTC_ERROR_RETURN(_sys_at_datapath_epe_xg_lg_enable(lchip, core_id, pp_id, dp_id));

    CTC_ERROR_RETURN(_sys_at_datapath_set_epe_wrr_weight(lchip, core_id, pp_id, dp_id));

    CTC_ERROR_RETURN(_sys_at_datapath_epe_misc_port_id_cfg(lchip, core_id, pp_id, dp_id));

    //CTC_ERROR_RETURN(_sys_at_datapath_epe_extra_cfg(lchip, core_id));

    return CTC_E_NONE;
}

int32
_sys_at_qmgr_speed_to_credit(uint8 lchip, uint16 speed)
{
    uint32 credit = 0;
    uint16 core_pll = 0;

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_core_pll(lchip, &core_pll, 1));

    if (900 == core_pll)
    {
        credit =
            (speed>=800) ? 81  :
            (speed>=400) ? 63  :
            (speed>=300) ? 47  :
            (speed>=200) ? 32  :
            (speed>=100) ? 26  :
            (speed>=50)  ? 20  :
            (speed>0)    ? 20  : 0;
    }
    else
    {
        credit =
            (speed>=800) ? 62  :
            (speed>=400) ? 48  :
            (speed>=300) ? 36  :
            (speed>=200) ? 24  :
            (speed>=100) ? 20  :
            (speed>=50)  ? 15  :
            (speed>0)    ? 15  : 0;
    }

    return credit;
}


int32
_sys_at_datapath_set_qmgr_credit(uint8 lchip, sys_dmps_db_chan_info_t* chan_info)
{    
    uint8  pp_chan_id   = 0;
    uint8  core_id      = 0;
    uint8  pp_id        = 0;
    uint8  core         = 0;
    uint32 index        = 0;
    uint32 speed        = 0;
    uint32 speed_tmp    = 0;
    uint32 cmd          = 0;
    DsQMgrChanCreditThrd_m    qmgr_credit;

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    CTC_PTR_VALID_CHECK(chan_info);
    core_id      = chan_info->core_id;
    pp_id        = chan_info->pp_id;

    pp_chan_id = chan_info->sub_chan_id + chan_info->dp_id * SYS_AT_CHAN_NUM_PER_DP;

    SYS_DATAPATH_SYS_MODE_TO_SPEED(chan_info->speed_mode, speed_tmp);
    speed = _sys_at_qmgr_speed_to_credit(lchip, speed_tmp);

    /* local core */
    /* DsQMgrChanCredit_t is pp level table */
    core  = core_id;
    index = DRV_INS(0, pp_chan_id);
    cmd   = DRV_IOR(DsQMgrChanCreditThrd_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &qmgr_credit));

    DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, DsQMgrChanCreditThrd_t, 0,
        pp_chan_id, DsQMgrChanCreditThrd_creditThrd_f, &speed, &qmgr_credit);
    
    cmd = DRV_IOW(DsQMgrChanCreditThrd_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &qmgr_credit));

    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        /* remote core */
        /* DsQMgrChanCredit_t is pp level table */
        core  = (0 == core_id) ? 1 : 0;
        index = DRV_INS(1, pp_chan_id);
        cmd   = DRV_IOR(DsQMgrChanCreditThrd_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &qmgr_credit));

        DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, DsQMgrChanCreditThrd_t, 1,
            pp_chan_id, DsQMgrChanCreditThrd_creditThrd_f, &speed, &qmgr_credit);
        
        cmd = DRV_IOW(DsQMgrChanCreditThrd_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &qmgr_credit));
    }

    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_qmgr_xg_lg_enable(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id)
{
    uint8   sub_chan_id  = 0;
    uint8   chan_idx     = 0;
    uint8   core         = 0;
    uint16  chan_id      = 0;
    uint16  speed        = 0;
    uint32  index        = 0;
    uint32  cmd          = 0;
    uint32  xg_bitmap    = 0;
    uint32  lg_bitmap    = 0;
    uint32  step         = 0;
    uint16 chan_list[SYS_AT_CHAN_NUM_PER_DP]  = {0};
    sys_dmps_db_chan_info_t chan_info         = {0};
    QMgrDeqChanIdCfg_m   qmgr_deq_cfg;

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    /* local core */
    core  = core_id;
    index = DRV_INS(0, 0);
    cmd   = DRV_IOR(QMgrDeqChanIdCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &qmgr_deq_cfg));

    CTC_ERROR_RETURN(_sys_at_datapath_get_dp_chan(lchip, core_id, pp_id, dp_id, chan_list, CHAN_DIR_TX));

    for (chan_idx = 0; chan_idx < SYS_AT_CHAN_NUM_PER_DP; chan_idx++)
    {
        chan_id = chan_list[chan_idx];
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id));
        chan_info.chan_id = chan_id;
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, &chan_info, CHAN_DIR_TX));
        SYS_DATAPATH_SYS_MODE_TO_SPEED(chan_info.speed_mode, speed);
        sub_chan_id = chan_info.sub_chan_id;

        if(speed < 50)
        {
            CTC_BIT_SET(xg_bitmap, sub_chan_id);
            CTC_BIT_UNSET(lg_bitmap, sub_chan_id);
        }
        else
        {
            CTC_BIT_SET(lg_bitmap, sub_chan_id);
            CTC_BIT_UNSET(xg_bitmap, sub_chan_id);
        }
    }

    step = QMgrDeqChanIdCfg_gDp_1_cfgLGChanEn_f - QMgrDeqChanIdCfg_gDp_0_cfgLGChanEn_f;
    DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, QMgrDeqChanIdCfg_t, 0, 0,
        QMgrDeqChanIdCfg_gDp_0_cfgLGChanEn_f + step * dp_id, &lg_bitmap, &qmgr_deq_cfg);
    step = QMgrDeqChanIdCfg_gDp_1_cfgXGChanEn_f - QMgrDeqChanIdCfg_gDp_0_cfgXGChanEn_f;
    DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, QMgrDeqChanIdCfg_t, 0, 0,
        QMgrDeqChanIdCfg_gDp_0_cfgXGChanEn_f + step * dp_id, &xg_bitmap, &qmgr_deq_cfg);

    cmd = DRV_IOW(QMgrDeqChanIdCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &qmgr_deq_cfg));

    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        /* remote core */
        core  = (0 == core_id) ? 1 : 0;
        index = DRV_INS(1, 0);
        cmd   = DRV_IOR(QMgrDeqChanIdCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &qmgr_deq_cfg));

        CTC_ERROR_RETURN(_sys_at_datapath_get_dp_chan(lchip, core_id, pp_id, dp_id, chan_list, CHAN_DIR_TX));

        for (chan_idx = 0; chan_idx < SYS_AT_CHAN_NUM_PER_DP; chan_idx++)
        {
            chan_id = chan_list[chan_idx];
            SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id));
            chan_info.chan_id = chan_id;
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, &chan_info, CHAN_DIR_TX));
            SYS_DATAPATH_SYS_MODE_TO_SPEED(chan_info.speed_mode, speed);
            sub_chan_id = chan_info.sub_chan_id;

            if(speed < 50)
            {
                CTC_BIT_SET(xg_bitmap, sub_chan_id);
                CTC_BIT_UNSET(lg_bitmap, sub_chan_id);
            }
            else
            {
                CTC_BIT_SET(lg_bitmap, sub_chan_id);
                CTC_BIT_UNSET(xg_bitmap, sub_chan_id);
            }
        }

        step = QMgrDeqChanIdCfg_gDp_1_cfgLGChanEn_f - QMgrDeqChanIdCfg_gDp_0_cfgLGChanEn_f;
        DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, QMgrDeqChanIdCfg_t, 1, 0,
            QMgrDeqChanIdCfg_gDp_0_cfgLGChanEn_f + step * dp_id, &lg_bitmap, &qmgr_deq_cfg);
        step = QMgrDeqChanIdCfg_gDp_1_cfgXGChanEn_f - QMgrDeqChanIdCfg_gDp_0_cfgXGChanEn_f;
        DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, QMgrDeqChanIdCfg_t, 1, 0,
            QMgrDeqChanIdCfg_gDp_0_cfgXGChanEn_f + step * dp_id, &xg_bitmap, &qmgr_deq_cfg);

        cmd = DRV_IOW(QMgrDeqChanIdCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &qmgr_deq_cfg));
    }

    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

int32
_sys_at_qmgr_write_weight_to_register(uint8 lchip, uint8 core_id, uint8 pp_id, uint16* weight_arr, uint16 (*xg_lg)[2])
{
    uint8  dp_id      = 0;
    uint8  core       = 0;
    uint16 divisor    = 0;
    uint16 pp_chan_id = 0;
    uint32 index      = 0;
    uint32 cmd        = 0;
    uint32 step       = 0;
    uint32 opt_weight = 0;
    uint16 weight_dp[AT_DP_NUM_PER_PP] = {0};
    QMgrDeqIntfWeightCfg_m  intf_weight_cfg;
    DsQMgrChanWeight_m      chan_weight;

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    weight_dp[0] += xg_lg[0][0];
    weight_dp[0] += xg_lg[0][1];
    weight_dp[1] += xg_lg[1][0];
    weight_dp[1] += xg_lg[1][1];

    /* local core */
    core  = core_id;
    /*  XG&LG Level WRR     256Depth  */
    CTC_ERROR_RETURN(sys_usw_datapath_get_gcd(weight_arr, SYS_AT_CHAN_NUM_PER_PP, &divisor));
    for(pp_chan_id = 0; pp_chan_id < SYS_AT_CHAN_NUM_PER_PP; pp_chan_id++)
    {
        index = DRV_INS(0, pp_chan_id);
        cmd = DRV_IOR(DsQMgrChanWeight_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &chan_weight));

        opt_weight = weight_arr[pp_chan_id] / divisor;

        DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, DsQMgrChanWeight_t, 0, pp_chan_id,
            DsQMgrChanWeight_weight_f, &opt_weight, &chan_weight);
        cmd = DRV_IOW(DsQMgrChanWeight_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &chan_weight));
    }

    /*  DP WRR  */
    index = DRV_INS(0, 0);
    cmd = DRV_IOR(QMgrDeqIntfWeightCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &intf_weight_cfg));
    for(dp_id = 0; dp_id < AT_DP_NUM_PER_PP; dp_id++)
    {
        CTC_ERROR_RETURN(sys_usw_datapath_get_gcd(xg_lg[dp_id], 2, &divisor));

        /* xg weight config per dp */
        opt_weight = xg_lg[dp_id][0] / divisor;
        step       = QMgrDeqIntfWeightCfg_gDp_1_cfgXgWeight_f - QMgrDeqIntfWeightCfg_gDp_0_cfgXgWeight_f;
        DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, QMgrDeqIntfWeightCfg_t, 0, 0,
            QMgrDeqIntfWeightCfg_gDp_0_cfgXgWeight_f + step * dp_id, &opt_weight, &intf_weight_cfg);

        /* lg weight config per dp */
        opt_weight = xg_lg[dp_id][1] / divisor;
        step       = QMgrDeqIntfWeightCfg_gDp_1_cfgLgWeight_f - QMgrDeqIntfWeightCfg_gDp_0_cfgLgWeight_f;
        DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, QMgrDeqIntfWeightCfg_t, 0, 0,
            QMgrDeqIntfWeightCfg_gDp_0_cfgLgWeight_f + step * dp_id, &opt_weight, &intf_weight_cfg);
    }

    /*  Slice WRR  */
    CTC_ERROR_RETURN(sys_usw_datapath_get_gcd(weight_dp, 2, &divisor));    
    opt_weight = weight_dp[0] /divisor;
    opt_weight = (0 == opt_weight) ? 1 : opt_weight;
    DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, QMgrDeqIntfWeightCfg_t, 0, 0,
        QMgrDeqIntfWeightCfg_cfgDp0Weight_f, &opt_weight, &intf_weight_cfg);
    opt_weight = weight_dp[1] /divisor;
    opt_weight = (0 == opt_weight) ? 1 : opt_weight;
    DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, QMgrDeqIntfWeightCfg_t, 0, 0,
        QMgrDeqIntfWeightCfg_cfgDp1Weight_f, &opt_weight, &intf_weight_cfg);

    cmd = DRV_IOW(QMgrDeqIntfWeightCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &intf_weight_cfg));

    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        /* remote core */
        core  = (0 == core_id) ? 1 : 0;
        /*  XG&LG Level WRR  */
        CTC_ERROR_RETURN(sys_usw_datapath_get_gcd(weight_arr, SYS_AT_CHAN_NUM_PER_PP, &divisor));
        for(pp_chan_id = 0; pp_chan_id < SYS_AT_CHAN_NUM_PER_PP; pp_chan_id++)
        {
            index = DRV_INS(1, pp_chan_id);
            cmd = DRV_IOR(DsQMgrChanWeight_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &chan_weight));

            opt_weight = weight_arr[pp_chan_id] / divisor;

            DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, DsQMgrChanWeight_t, 1, pp_chan_id,
                DsQMgrChanWeight_weight_f, &opt_weight, &chan_weight);
            cmd = DRV_IOW(DsQMgrChanWeight_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &chan_weight));
        }

        /*  DP WRR  */
        index = DRV_INS(1, 0);
        cmd = DRV_IOR(QMgrDeqIntfWeightCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &intf_weight_cfg));
        for(dp_id = 0; dp_id < AT_DP_NUM_PER_PP; dp_id++)
        {
            CTC_ERROR_RETURN(sys_usw_datapath_get_gcd(xg_lg[dp_id], 2, &divisor));

            /* xg weight config per dp */
            opt_weight = xg_lg[dp_id][0] / divisor;
            step       = QMgrDeqIntfWeightCfg_gDp_1_cfgXgWeight_f - QMgrDeqIntfWeightCfg_gDp_0_cfgXgWeight_f;
            DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, QMgrDeqIntfWeightCfg_t, 1, 0,
                QMgrDeqIntfWeightCfg_gDp_0_cfgXgWeight_f + step * dp_id, &opt_weight, &intf_weight_cfg);

            /* lg weight config per dp */
            opt_weight = xg_lg[dp_id][1] / divisor;
            step       = QMgrDeqIntfWeightCfg_gDp_1_cfgLgWeight_f - QMgrDeqIntfWeightCfg_gDp_0_cfgLgWeight_f;
            DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, QMgrDeqIntfWeightCfg_t, 1, 0,
                QMgrDeqIntfWeightCfg_gDp_0_cfgLgWeight_f + step * dp_id, &opt_weight, &intf_weight_cfg);
        }

        /*  Slice WRR  */
        CTC_ERROR_RETURN(sys_usw_datapath_get_gcd(weight_dp, 2, &divisor));    
        opt_weight = weight_dp[0] /divisor;
        opt_weight = (0 == opt_weight) ? 1 : opt_weight;
        DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, QMgrDeqIntfWeightCfg_t, 1, 0,
            QMgrDeqIntfWeightCfg_cfgDp0Weight_f, &opt_weight, &intf_weight_cfg);
        opt_weight = weight_dp[1] /divisor;
        opt_weight = (0 == opt_weight) ? 1 : opt_weight;
        DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, QMgrDeqIntfWeightCfg_t, 1, 0,
            QMgrDeqIntfWeightCfg_cfgDp1Weight_f, &opt_weight, &intf_weight_cfg);

        cmd = DRV_IOW(QMgrDeqIntfWeightCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &intf_weight_cfg));
    }

    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

/*
 * @brief       DsQMgrChanWeight -- weight
 *              QMgrDeqIntWeightCfg -- gDp_(0/1)_cfg(L/X)gWeight
 *                                 -- cfgDp(0/1)Weight 
 *              
 */
STATIC int32
_sys_at_datapath_set_qmgr_wrr_weight(uint8 lchip, uint8 core_id, uint8 pp_id)
{
    uint8  dp_id        = 0;
    uint8  chan_idx     = 0;
    uint16 xg_lg[2][2]  = {{0}};
    uint16 speed        = 0;
    uint16 chan_id      = 0;
    uint16 pp_chan_id   = 0;
    uint16 weight       = 0;
    uint16 weight_arr[SYS_AT_CHAN_NUM_PER_PP] = {0};
    uint16 chan_list[SYS_AT_CHAN_NUM_PER_PP]  = {0};
    sys_dmps_db_chan_info_t chan_info         = {0};

    /* network chan */
    for (chan_idx = 0; chan_idx < SYS_AT_NW_CHAN_NUM_PER_PP; chan_idx++)
    {
        chan_id = core_id * AT_NW_CHAN_NUM_PER_CORE + pp_id * SYS_AT_NW_CHAN_NUM_PER_PP + chan_idx;
        chan_list[chan_idx] = chan_id;
    }

    /* dp 0 chan 24 */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, 0, SYS_AT_MISC_CHAN_ID_IN_DP, &chan_id, CHAN_DIR_TX));
    chan_list[SYS_AT_NW_CHAN_NUM_PER_PP] = chan_id;

    /* dp 0 chan 25 */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, 0, SYS_AT_LOOP_CHAN_ID_IN_DP, &chan_id, CHAN_DIR_TX));
    chan_list[SYS_AT_NW_CHAN_NUM_PER_PP + 1] = chan_id;

    /* dp 1 chan 24 */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, 1, SYS_AT_MISC_CHAN_ID_IN_DP, &chan_id, CHAN_DIR_TX));
    chan_list[SYS_AT_NW_CHAN_NUM_PER_PP + 2] = chan_id;

    /* dp 1 chan 25 */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, 1, SYS_AT_LOOP_CHAN_ID_IN_DP, &chan_id, CHAN_DIR_TX));
    chan_list[SYS_AT_NW_CHAN_NUM_PER_PP + 3] = chan_id;

    for (chan_idx = 0; chan_idx < SYS_AT_CHAN_NUM_PER_PP; chan_idx++)
    {
        chan_id = chan_list[chan_idx];
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id));
        chan_info.chan_id = chan_id;
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, &chan_info, CHAN_DIR_TX));
        dp_id = chan_info.dp_id;
        SYS_DATAPATH_SYS_SPEED_TO_WRRCFG(chan_info.speed_mode, weight);
        SYS_DATAPATH_SYS_MODE_TO_SPEED(chan_info.speed_mode, speed);
        if(speed < 50)
        {
            xg_lg[dp_id][0]  += weight;
        }
        else
        {
            xg_lg[dp_id][1]  += weight;
        }
        pp_chan_id = chan_info.sub_chan_id + dp_id * SYS_AT_CHAN_NUM_PER_DP;
        weight_arr[pp_chan_id] = ((weight <= 250) ? 250 : ((weight <= 500) ? 500 : weight));
    }

    CTC_ERROR_RETURN(_sys_at_qmgr_write_weight_to_register(lchip, core_id, pp_id, weight_arr, xg_lg));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_qmgr_misc_en(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 en_flag)
{
    uint32 value   = ((TRUE == en_flag) ? 0xffffffff : 0x0);
    uint32 cmd     = 0;
    QMgrQueEntryMcDrainEnable_m qmgr_que;

    cmd    = DRV_IOR(QMgrQueEntryMcDrainEnable_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &qmgr_que));
    DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, QMgrQueEntryMcDrainEnable_t, 0,
        QMgrQueEntryMcDrainEnable_freePtrDrainEnable_f, &value, &qmgr_que);
    cmd    = DRV_IOW(QMgrQueEntryMcDrainEnable_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &qmgr_que));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_qmgr_deq_scan_bmp(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 pp_chan, uint32 value)
{
    uint8  cnt   = 0;
    uint8  core  = 0;
    uint32 cmd   = 0;
    uint32 index = 0;
    DsQMgrDeqScanBmp_m qmgr_scan_bmp;

    for (cnt = 0; cnt < 12; cnt++)
    {
        /* local core */
        core  = core_id;
        index = DRV_INS(0, pp_chan * 12 + cnt);

        cmd   = DRV_IOR(DsQMgrDeqScanBmp_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &qmgr_scan_bmp));
        DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, DsQMgrDeqScanBmp_t, 0, (pp_chan * 12 + cnt),
            DsQMgrDeqScanBmp_state_f, &value, &qmgr_scan_bmp);
        cmd   = DRV_IOW(DsQMgrDeqScanBmp_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &qmgr_scan_bmp));
    }

    if (SYS_AT_CHIP_IS_DC(lchip))
    {
        for (cnt = 0; cnt < 12; cnt++)
        {
            /* remote core */
            core  = (0 == core_id) ? 1 : 0;
            index = DRV_INS(1, pp_chan * 12 + cnt);
    
            cmd   = DRV_IOR(DsQMgrDeqScanBmp_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &qmgr_scan_bmp));
            DRV_IOW_ENTRY_NZ(core, pp_id, 0xff, lchip, DsQMgrDeqScanBmp_t, 1, (pp_chan * 12 + cnt),
                DsQMgrDeqScanBmp_state_f, &value, &qmgr_scan_bmp);
            cmd   = DRV_IOW(DsQMgrDeqScanBmp_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core, pp_id, cmd, &qmgr_scan_bmp));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_qmgr_common_calendar(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 *p_error,
                                        uint16 *p_walk_end, uint16 *p_cal, sys_at_cal_info_collect_t* cal_info)
{
    int32  ret                  = CTC_E_NONE;
    uint8  pp_chan_id           = 0;
    int16  cal_entry_num        = 512;
    uint32 speed                = 0;
    uint32 *speed_list          = NULL;

    SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);

    /*1. First Use new calendar algorithms*/
    sal_memset(p_cal, 0, SYS_AT_MAX_CAL_LEN * sizeof(uint16));
    *p_walk_end = 0;

    speed_list = (uint32*)mem_malloc(MEM_DMPS_MODULE, SYS_AT_CHAN_NUM_PER_PP * sizeof(uint32));
    if(NULL == speed_list)
    {
        return CTC_E_NO_MEMORY;
    }
    sal_memset(speed_list, 0, SYS_AT_CHAN_NUM_PER_PP * sizeof(uint32));

    for(pp_chan_id = 0; pp_chan_id < SYS_AT_CHAN_NUM_PER_PP; pp_chan_id ++)
    {
        speed = cal_info[pp_chan_id].speed;

        /* set network as 100G which less than 100G */
        if ((speed > 0) && (speed < 100))
        {
            speed = 100;
        }

        /* set misc and loop as 100G */
        if ((speed > 0) && 
            ((SYS_AT_MISC_CHAN_ID_IN_DP == pp_chan_id) || (SYS_AT_LOOP_CHAN_ID_IN_DP == pp_chan_id)
            || ((SYS_AT_MISC_CHAN_ID_IN_DP + SYS_AT_CHAN_NUM_PER_DP) == pp_chan_id)
            || ((SYS_AT_LOOP_CHAN_ID_IN_DP + SYS_AT_CHAN_NUM_PER_DP) == pp_chan_id)))
        {
            speed = 100;
        }

        speed_list[pp_chan_id] = speed;
    }

    /* stage3 : calculate calendar use common_calendar */
     CTC_ERROR_GOTO(_sys_at_datapath_common_calendar(cal_entry_num, SYS_AT_CHAN_NUM_PER_PP, speed_list, 
                                                         p_error, p_walk_end, p_cal), ret, RELEASE_PTR_RETURN);

RELEASE_PTR_RETURN:
    mem_free(speed_list);

    return ret;
}

int32
_sys_at_datapath_qmgr_calendar_write_to_register(uint8 lchip, uint8 core_id, uint8 pp_id, const uint16* cal, uint16 walk_end)
{
    uint8  is_back_cal = 0;
    uint16 i       = 0;
    uint32 val_32  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    QMgrSchCalendar0_m qmgr_cal;
    QMgrSchCalCtl_m    qmgr_cal_ctl;

    index = DRV_INS(0, 0);
    
    cmd = DRV_IOR(QMgrSchCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &qmgr_cal_ctl));

    val_32 = GetQMgrSchCalCtl(V, cfgCalUsedEn_f, &qmgr_cal_ctl);
    is_back_cal = GetQMgrSchCalCtl(V, cfgCalSel_f, &qmgr_cal_ctl);
    if(val_32 == 0)
    {
        is_back_cal = 0;
    }
    else
    {
        is_back_cal = is_back_cal ? 0 : 1;
    }

    /* Entry */
    tbl_id = (is_back_cal ? QMgrSchCalendar1_t : QMgrSchCalendar0_t);
    fld_id = (is_back_cal ? QMgrSchCalendar1_chan_f : QMgrSchCalendar0_chan_f);

    for(i = 0; i <= walk_end; i++)
    {       
        index = DRV_INS(0, i);

        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &qmgr_cal));

        val_32 = cal[i];
        DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, tbl_id, 0, i, fld_id, &val_32, &qmgr_cal);

        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &qmgr_cal));
    }

    /* cfg 0x3f with invalid */
    for (i = walk_end + 1; i < 52; i++)
    {
        index = DRV_INS(0, i);

        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &qmgr_cal));

        val_32 = 0x3f;
        DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, tbl_id, 0, i, fld_id, &val_32, &qmgr_cal);

        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &qmgr_cal));
    }

    /* WalkerEnd: force to config 51 */
    val_32 = 51;
    if(is_back_cal)
    {
        DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, QMgrSchCalCtl_t, 0, 0, QMgrSchCalCtl_cfgCal1WalkEndPtr_f, &val_32, &qmgr_cal_ctl);
    }
    else
    {
        DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, QMgrSchCalCtl_t, 0, 0, QMgrSchCalCtl_cfgCal0WalkEndPtr_f, &val_32, &qmgr_cal_ctl);
    }
    index = DRV_INS(0, 0);
    cmd = DRV_IOW(QMgrSchCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &qmgr_cal_ctl));

    /* BankSel */
    cmd = DRV_IOR(QMgrSchCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &qmgr_cal_ctl));
    val_32 = 1;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, QMgrSchCalCtl_t, 0, 0, QMgrSchCalCtl_cfgCalUsedEn_f, &val_32, &qmgr_cal_ctl);
    val_32 = is_back_cal;
    DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, QMgrSchCalCtl_t, 0, 0, QMgrSchCalCtl_cfgCalSel_f, &val_32, &qmgr_cal_ctl);
    cmd = DRV_IOW(QMgrSchCalCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &qmgr_cal_ctl));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_qmgr_calendar(uint8 lchip, uint8 core_id, uint8 pp_id)
{
    int32   ret      = CTC_E_NONE;
    uint8   error    = TRUE;
    uint16* cal      = NULL;
    uint16  walk_end = 0;
    sys_at_cal_info_collect_t* cal_info = NULL;

    cal = (uint16*)mem_malloc(MEM_DMPS_MODULE, SYS_AT_MAX_CAL_LEN * sizeof(uint16));
    CTC_ERROR_GOTO((NULL == cal) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_1);
    sal_memset(cal, 0xff, SYS_AT_MAX_CAL_LEN * sizeof(uint16));

    cal_info = (sys_at_cal_info_collect_t*)mem_malloc(MEM_DMPS_MODULE,
        SYS_AT_CHAN_NUM_PER_PP * sizeof(sys_at_cal_info_collect_t));
    CTC_ERROR_GOTO((NULL == cal_info) ? CTC_E_NO_MEMORY : CTC_E_NONE, ret, RELEASE_PTR_RETURN_2);

    /* 1.  set Qmgr calendar, consider CPUMAC */
    /* 1.1 info collect */
    _sys_at_calendar_speed_info_collect(lchip, cal_info, core_id, pp_id, DMPS_INVALID_VALUE_U8, DMPS_INVALID_VALUE_U8, SYS_AT_QMGR_CAL);
    /* 1.2 calender caculateion */
    CTC_ERROR_GOTO(_sys_at_datapath_qmgr_common_calendar(lchip, core_id, pp_id, &error, &walk_end, cal, cal_info), 
        ret, RELEASE_PTR_RETURN_3);
    /* 1.3 config register */
    if(SYS_AT_MAX_CAL_LEN > walk_end)
    {
        CTC_ERROR_GOTO(_sys_at_datapath_qmgr_calendar_write_to_register(lchip, core_id, pp_id, cal, walk_end), 
            ret, RELEASE_PTR_RETURN_3);
    }

RELEASE_PTR_RETURN_3:
    mem_free(cal_info);
RELEASE_PTR_RETURN_2:
    mem_free(cal);
RELEASE_PTR_RETURN_1:
    return ret;
}

int32
_sys_at_datapath_qmgr_init(uint8 lchip, uint8 core_id, uint8 pp_id)
{
    uint8  dp_id      = 0;
    uint16 start_chan = 0;
    uint16 end_chan   = 0;
    uint16 chan_id    = 0;
    sys_dmps_db_chan_info_t chan_info = {0};

    CTC_ERROR_RETURN(_sys_at_datapath_set_qmgr_calendar(lchip, core_id, pp_id));

    start_chan = core_id * AT_NW_CHAN_NUM_PER_CORE + pp_id * SYS_AT_NW_CHAN_NUM_PER_PP;
    end_chan   = start_chan + SYS_AT_NW_CHAN_NUM_PER_PP;

    for (chan_id = start_chan; chan_id < end_chan; chan_id++)
    {
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id));

        chan_info.chan_id = chan_id;
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, &chan_info, CHAN_DIR_TX));
        CTC_ERROR_RETURN(_sys_at_datapath_set_qmgr_credit(lchip, &chan_info));
    }

    /* dp 0 misc chan */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, 0, SYS_AT_MISC_CHAN_ID_IN_DP, &chan_id, CHAN_DIR_TX));
    if (sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id))
    {
        chan_info.chan_id = chan_id;
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, &chan_info, CHAN_DIR_TX));
        CTC_ERROR_RETURN(_sys_at_datapath_set_qmgr_credit(lchip, &chan_info));
    }

    /* dp 0 loop chan */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, 0, SYS_AT_LOOP_CHAN_ID_IN_DP, &chan_id, CHAN_DIR_TX));
    if (sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id))
    {
        chan_info.chan_id = chan_id;
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, &chan_info, CHAN_DIR_TX));
        CTC_ERROR_RETURN(_sys_at_datapath_set_qmgr_credit(lchip, &chan_info));
    }

    /* dp 1 misc chan */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, 1, SYS_AT_MISC_CHAN_ID_IN_DP, &chan_id, CHAN_DIR_TX));
    if (sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id))
    {
        chan_info.chan_id = chan_id;
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, &chan_info, CHAN_DIR_TX));
        CTC_ERROR_RETURN(_sys_at_datapath_set_qmgr_credit(lchip, &chan_info));
    }

    /* dp 1 loop chan */
    CTC_ERROR_RETURN(_sys_at_datapath_get_misc_loop_chan(lchip, core_id, pp_id, 1, SYS_AT_LOOP_CHAN_ID_IN_DP, &chan_id, CHAN_DIR_TX));
    if (sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id))
    {
        chan_info.chan_id = chan_id;
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, &chan_info, CHAN_DIR_TX));
        CTC_ERROR_RETURN(_sys_at_datapath_set_qmgr_credit(lchip, &chan_info));
    }

    for(dp_id = 0; dp_id < AT_DP_NUM_PER_PP; dp_id++)
    {
        /*set qmgr xg lg chan en*/
        CTC_ERROR_RETURN(_sys_at_datapath_set_qmgr_xg_lg_enable(lchip, core_id, pp_id, dp_id));
    }

    /* one pp calculated together */
    CTC_ERROR_RETURN(_sys_at_datapath_set_qmgr_wrr_weight(lchip, core_id, pp_id));

    /*QMgrMsgMiscDrainEnable.freePtrDrainEnable set 1*/
    CTC_ERROR_RETURN(_sys_at_datapath_set_qmgr_misc_en(lchip, core_id, pp_id, TRUE));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_resource_alloc_chan(uint8 lchip, uint16 chan_id, uint8 enable, uint8 dir_bmp, uint8 cfg_nettx_credit)
{
    sys_dmps_db_chan_info_t chan_info = {0};

    chan_info.chan_id = chan_id;

    if (CHAN_DIR_IS_TX(dir_bmp))
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, &chan_info, CHAN_DIR_TX));
        if (DMPS_INVALID_VALUE_U8 != chan_info.txqm_id)
        {
            /* network port */
            /*set Epe credit*/
            CTC_ERROR_RETURN(_sys_at_datapath_set_epe_credit(lchip, &chan_info));

            /* set nettx timer en */
            CTC_ERROR_RETURN(_sys_at_datapath_nettx_timer_en(lchip, &chan_info, enable));

            if (cfg_nettx_credit)
            {
                /*set NetTx credit*/
                CTC_ERROR_RETURN(_sys_at_datapath_set_nettx_credit_thrd(lchip, &chan_info));
            }
        }

        CTC_ERROR_RETURN(_sys_at_datapath_set_br_mode(lchip, &chan_info));
        CTC_ERROR_RETURN(_sys_at_datapath_set_bs_mode(lchip, &chan_info));

        /*set BufRetrv credit*/
        CTC_ERROR_RETURN(_sys_at_datapath_set_bufretrv_credit(lchip, &chan_info));

        /*set Qmgr credit*/
        CTC_ERROR_RETURN(_sys_at_datapath_set_qmgr_credit(lchip, &chan_info));
    }

    if (CHAN_DIR_IS_RX(dir_bmp))
    {
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, &chan_info, CHAN_DIR_RX));
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_resource_alloc_group(uint8 lchip, uint8 core_id, uint8 pp_id, uint8 dp_id, uint8 txqm_id, uint8 is_nw, uint8 dir_bmp)
{
    /*set Epe, NetRx, BufRetrv calendar*/
    CTC_ERROR_RETURN(_sys_at_datapath_set_general_calendar(lchip, core_id, pp_id, dp_id, dir_bmp));

    if (CHAN_DIR_IS_TX(dir_bmp))
    {
        if (is_nw)
        {
            /*set NetTx calendar*/
            CTC_ERROR_RETURN(_sys_at_datapath_set_nettx_calendar(lchip, core_id, pp_id, dp_id, txqm_id));
        }

        /*set Qmgr calendar*/
        CTC_ERROR_RETURN(_sys_at_datapath_set_qmgr_calendar(lchip, core_id, pp_id));

        /*set bufRetrv wrr weight*/
        CTC_ERROR_RETURN(_sys_at_datapath_set_bufretrv_wrr_weight(lchip, core_id, pp_id, dp_id));

        /*set Epe xg lg enable*/
        CTC_ERROR_RETURN(_sys_at_datapath_epe_xg_lg_enable(lchip, core_id, pp_id, dp_id));

        /*set Epe wrr weight*/
        CTC_ERROR_RETURN(_sys_at_datapath_set_epe_wrr_weight(lchip, core_id, pp_id, dp_id));

        /*set Qmgr xg lg enable*/
        CTC_ERROR_RETURN(_sys_at_datapath_set_qmgr_xg_lg_enable(lchip, core_id, pp_id, dp_id));

        /*set Qmgr wrr weight*/
        CTC_ERROR_RETURN(_sys_at_datapath_set_qmgr_wrr_weight(lchip, core_id, pp_id));
    }

    if (CHAN_DIR_IS_RX(dir_bmp))
    {
        /*set NetRx wrr weight*/
        CTC_ERROR_RETURN(_sys_at_datapath_set_dp_netrx_wrr_weight(lchip, core_id, pp_id, dp_id));

        /*set NetRx buf*/
        CTC_ERROR_RETURN(_sys_at_datapath_set_dp_netrx_buf(lchip, core_id, pp_id, dp_id));
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_dynamic_switch_dp(uint8 lchip, sys_dmps_ds_list_t* target, uint8 dir_flag)
{
    uint8  core_id  = 0;
    uint8  pp_id    = 0;
    uint8  dp_id    = 0;
    uint8  txqm_id  = 0;
    uint8  chan_num = 0;
    uint8  sub_chan = 0;
    uint16 chan_id  = 0;
    uint16 dport    = 0;
    uint16 lsd      = 0;
    sys_dmps_db_upt_info_t port_info  = {0};

    if (0 == target->chan_info.dst_chan_num)
    {
        chan_id = target->chan_info.src_chan_list[0];
    }
    else
    {
        chan_id = target->chan_info.dst_chan_list[0];
    }

    SYS_CONDITION_RETURN(!sys_usw_dmps_db_is_usable_id(lchip, DMPS_DB_TYPE_CHAN, chan_id), CTC_E_INVALID_CONFIG);
    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_PP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_DP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_TXQM_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SUB_CHAN_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,     core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_PP_ID,       pp_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_DP_ID,       dp_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_TXQM_ID,     txqm_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID, sub_chan);

    /* 1. resource alloc by group */
    CTC_ERROR_RETURN(_sys_at_datapath_resource_alloc_group(lchip, core_id, pp_id, dp_id, txqm_id,
        SYS_AT_IS_NW_CHAN(sub_chan), CHAN_DIR_TXRX));

    /* 2. resource alloc by chan */
    if (dir_flag)
    {
        /* dynamic_switch from none */
        for (chan_num = 0; chan_num < target->chan_info.dst_chan_num; chan_num++)
        {
            chan_id = target->chan_info.dst_chan_list[chan_num];
            CTC_ERROR_RETURN(_sys_at_datapath_resource_alloc_chan(lchip, chan_id, TRUE, CHAN_DIR_TXRX, TRUE));

            CTC_ERROR_RETURN(sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_CHAN, chan_id, DMPS_DB_TYPE_LSD, NULL, &lsd));
            CTC_ERROR_RETURN(_sys_at_datapath_get_port_chan_by_serdes(lchip, lsd, NULL, &dport));
            if (DMPS_INVALID_VALUE_U16 != dport)
            {
                CTC_ERROR_RETURN(_sys_at_datapath_map(lchip, dport, chan_id, CHAN_DIR_TXRX));
            }
        }
    }
    else
    {
        /* dynamic_switch to none */
        for (chan_num = 0; chan_num < target->chan_info.src_chan_num; chan_num++)
        {
            chan_id = target->chan_info.src_chan_list[chan_num];
            
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SUB_CHAN_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID, sub_chan);

            CTC_ERROR_RETURN(_sys_at_datapath_resource_alloc_chan(lchip, chan_id, FALSE, CHAN_DIR_TXRX, TRUE));

            /* clear DsQMgrDeqScanBmp */
            CTC_ERROR_RETURN(_sys_at_datapath_set_qmgr_deq_scan_bmp(lchip, core_id, pp_id,
                dp_id * SYS_AT_CHAN_NUM_PER_DP + sub_chan, 0));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_xpipe_resource_alloc(uint8 lchip, uint16 dport, uint8 chan_num, uint16* chan_list, uint8 dir_bmp)
{
    uint8  cnt      = 0;
    uint8  core_id  = 0;
    uint8  pp_id    = 0;
    uint8  dp_id    = 0;
    uint8  txqm_id  = 0;
    uint16 chan_id  = 0;
    sys_dmps_db_upt_info_t port_info  = {0};
    sys_dmps_db_chan_info_t chan_info = {0};

    if (NULL == chan_list)
    {
        return CTC_E_INVALID_PARAM;
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT, dport);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_PP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_DP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_TXQM_ID);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,     core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_PP_ID,       pp_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_DP_ID,       dp_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_TXQM_ID,     txqm_id);

    /* 1. resource alloc by group */
    CTC_ERROR_RETURN(_sys_at_datapath_resource_alloc_group(lchip, core_id, pp_id, dp_id, txqm_id, TRUE, dir_bmp));

    for (cnt = 0; cnt < chan_num; cnt++)
    {
        chan_id = chan_list[cnt];
        chan_info.chan_id = chan_id;
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, &chan_info, dir_bmp));

        /* 2. resource alloc by chan */
        CTC_ERROR_RETURN(_sys_at_datapath_resource_alloc_chan(lchip, chan_id, TRUE, dir_bmp, FALSE));

        /*3. cfg mapping */
        CTC_ERROR_RETURN(_sys_at_datapath_map_by_chan(lchip, dport, chan_id, dir_bmp));

        CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_uc(lchip, cnt, chan_list[0],
            ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (chan_info.sub_chan_id & 0x1F), dir_bmp));
        /* If chan_num is 1, config UcQWritePortChannelMap_g_1/2_channelId the same as that of UcQWritePortChannelMap_g_0_channelId */
        if (1 == chan_num)
        {
            CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_uc(lchip, 1, chan_list[0],
                ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (chan_info.sub_chan_id & 0x1F), dir_bmp));
            CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_uc(lchip, 2, chan_list[0],
                ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (chan_info.sub_chan_id & 0x1F), dir_bmp));
        }
        /* If chan_num is 2, config UcQWritePortChannelMap_g_2_channelId the same as that of UcQWritePortChannelMap_g_1_channelId */
        else if ((2 == chan_num) && (1 == cnt))
        {
            CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_uc(lchip, 2, chan_list[0],
                ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (chan_info.sub_chan_id & 0x1F), dir_bmp));
        }

        /* if chan_num is 2, config priority 1 and priority 0 */
        if (2 == chan_num)
        {
            CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_mc(lchip, cnt, chan_list[0],
                ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (chan_info.sub_chan_id & 0x1F), dir_bmp));
        }
        /* if chan_num is 1 or 3, config priority 1 the same as priority 0 */
        else if (cnt == 0)
        {
            CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_mc(lchip, 0, chan_list[0],
                ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (chan_info.sub_chan_id & 0x1F), dir_bmp));
            CTC_ERROR_RETURN(_sys_at_datapath_map_sub_chan_mc(lchip, 1, chan_list[0],
                ((core_id & 0x1) << 8) | ((pp_id & 0x3) << 6) | ((dp_id & 0x1) << 5) | (chan_info.sub_chan_id & 0x1F), dir_bmp));
        }
    }

    return CTC_E_NONE;
}

int32
sys_at_datapath_set_other_misc_chan(uint8 lchip, uint16 lport, uint8 port_type, uint8 speed_mode, uint8 dir_bmp)
{
    uint8  core_num     = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;
    uint8  core_id      = 0;
    uint8  pp_id        = 0;
    uint8  dp_id        = 0;
    uint8  txqm_id      = 0;
    uint8  find_flag    = FALSE;
    uint16 p_chan       = SYS_AT_USELESS_ID16;
    uint16 p_sub_chan   = SYS_AT_USELESS_ID16;
    uint16 p_mac_client = SYS_AT_USELESS_ID16;
    uint16 dport        = lport;
    uint32 speed_value  = 0;
    sys_dmps_db_upt_info_t port_info = {0};

    CTC_ERROR_RETURN((sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport)) ? CTC_E_INVALID_PORT : CTC_E_NONE);

    /* 1. get free chan */
    for (core_id = 0; core_id < core_num; core_id++)
    {
        for (pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));
            for (dp_id = 0; dp_id < AT_DP_NUM_PER_PP; dp_id++)
            {
                for(txqm_id = 0; txqm_id < SYS_AT_TXQM_NUM_PER_DP; txqm_id++)
                {
                    if (CTC_E_NONE == _sys_at_datapath_get_free_chan(lchip, core_id, pp_id, dp_id, txqm_id,
                                        1, &p_chan, &p_sub_chan, &p_mac_client, dir_bmp))
                    {
                        find_flag = TRUE;
                        break;
                    }
                }
                if (find_flag)
                {
                    break;
                }
            }
            if (find_flag)
            {
                break;
            }
        }
        if (find_flag)
        {
            break;
        }
    }

    if (!find_flag)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "%% There is no free channel! \n");
        return CTC_E_NO_RESOURCE;
    }

    /* 2. Update DMPS DB */
    SYS_USW_GET_SPEED_VALUE(speed_mode, SYS_DMPS_FEC_TYPE_NONE, CTC_CHIP_SERDES_OCS_MODE_NONE, speed_value);

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_UPDATE(port_info);
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_DPORT,           dport);
    DMPS_DB_SET_MAP_INFO(port_info, GET_CHAN_ID_BY_DIR(dir_bmp), p_chan);
    DMPS_DB_SET_PROPERTY_INFO(port_info, GET_SPEED_VALUE_BY_DIR(dir_bmp),      speed_value);
    DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,             port_type);
    DMPS_DB_SET_PROPERTY_INFO(port_info, GET_CORE_ID_BY_DIR(dir_bmp),       core_id);
    DMPS_DB_SET_PROPERTY_INFO(port_info, GET_PP_ID_BY_DIR(dir_bmp),         pp_id);
    DMPS_DB_SET_PROPERTY_INFO(port_info, GET_DP_ID_BY_DIR(dir_bmp),         dp_id);
    DMPS_DB_SET_PROPERTY_INFO(port_info, GET_TXQM_ID_BY_DIR(dir_bmp),       txqm_id);
    DMPS_DB_SET_PROPERTY_INFO(port_info, GET_SPEED_MODE_BY_DIR(dir_bmp),    speed_mode);
    DMPS_DB_SET_PROPERTY_INFO(port_info, GET_MAC_CLIENT_ID_BY_DIR(dir_bmp), p_mac_client);
    DMPS_DB_SET_PROPERTY_INFO(port_info, GET_SUB_CHAN_ID_BY_DIR(dir_bmp),   p_sub_chan);
    CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &port_info));

    CTC_ERROR_RETURN(sys_usw_dmps_db_assign_chan_by_dir(lchip, p_chan, dir_bmp));
    CTC_ERROR_RETURN(sys_usw_dmps_db_assign_port(lchip, lport));

    CTC_ERROR_RETURN(sys_usw_dmps_db_set_ext_lport_map(lchip, lport, dport));

    /* 3. resource alloc */
    CTC_ERROR_RETURN(_sys_at_datapath_resource_alloc_group(lchip, core_id, pp_id, dp_id, txqm_id, FALSE, dir_bmp));
    CTC_ERROR_RETURN(_sys_at_datapath_resource_alloc_chan(lchip, p_chan, TRUE, dir_bmp, TRUE));

    CTC_ERROR_RETURN(_sys_at_datapath_map_by_port(lchip, dport, p_chan, dir_bmp));
    CTC_ERROR_RETURN(_sys_at_datapath_map_by_chan(lchip, dport, p_chan, dir_bmp));

    return CTC_E_NONE;
}

int32
_sys_at_datapath_set_priority(uint8 lchip, uint16 chan_id, uint8 enable)
{
    sys_dmps_db_chan_info_t chan_info = {0};
    sys_dmps_db_upt_info_t port_info  = {0};

    chan_info.chan_id = chan_id;
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_chan_info(lchip, &chan_info, CHAN_DIR_TX));

    if ((enable && chan_info.prio) || ((!enable) && (!(chan_info.prio))))
    {
        return CTC_E_NONE;
    }

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID,           chan_id);
    DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_PRIO,  (enable ? TRUE : FALSE));
    CTC_ERROR_RETURN(sys_usw_dmps_db_set_port_info(lchip, &port_info));

    CTC_ERROR_RETURN(_sys_at_datapath_set_bufretrv_credit(lchip, &chan_info));

    return CTC_E_NONE;
}

int32
sys_at_datapath_set_priority(uint8 lchip, uint16 dport, uint32 value)
{
    uint8  enable  = (value > 3) ? TRUE : FALSE;
    uint16 chan_id = 0;

    CTC_ERROR_RETURN(sys_usw_dmps_db_get_dport_relative_id(lchip, dport, DMPS_DB_TYPE_CHAN, &chan_id));
    CTC_ERROR_RETURN(_sys_at_datapath_set_priority(lchip, chan_id, enable));

    return CTC_E_NONE;
}

/*Register                                    Core/PP/DP          Value                             */
/*QMgrDeqChanIdCfg.cfgDmaChanEn               Get DB (write PEER) SYS_DMPS_DMA_PORT-1  other-0      */
/*QMgrDeqChanIdCfg.dmaExtEn                   Get DB (write PEER) SYS_DMPS_DMA_PORT-1  other-0      */
/*QMgrDeqChanIdCfg.cfgDmaChanId               Get DB (write PEER) sub_chan_id SYS_DMPS_MISC_SUB_CHAN*/
/*BufStoreProcMiscChanIdCfg.cfgDmaChanIdEn    Get DB              SYS_DMPS_DMA_PORT-1  other-0      */
/*BufStoreProcMiscChanIdCfg.cfgOamOrDmaChanId Get DB              sub_chan_id SYS_DMPS_MISC_SUB_CHAN*/
/*BufStoreProcMiscChanIdCfg.cfgMaxNetChanId   Get DB              SYS_DMPS_CPUMAC_NETWORK_PORT-24 other-23 */
/*BufStoreProcMiscChanIdCfg.cfgOamChanIdEn    Get DB              SYS_DMPS_OAM_PORT-1  other-0      */
/*DsChannelizeMode.portMaxLen                 ALL misc in ALL dp  16383, 9600 in entry 26           */
/*DsChannelizeMode.portMinLen                 ALL misc in ALL dp  33                                */
/*NetRxMiscChanIdCfg.cfgLogChanId             skip                skip, using default value         */
/*NetRxMiscCtl.cfgMiscType                    Get DB              OAM-0, DMA-1, CPUMAC-2            */
/*EpeScheduleMiscCtl.cfgMiscOutIntfSel        Get DB              OAM-0, DMA-1, CPUMAC-2            */
/*EpeScheduleCreditCtl.toMiscCreditThrd       Get DB              OAM-80, DMA-64, CPUMAC-128        */
int32
_sys_at_datapath_misc_port_cfg(uint8 lchip)
{
    uint8  port_type = SYS_DMPS_MAX_PORT_TYPE;
    uint8  pp_id     = 0; /*0~3*/
    uint8  core_id   = 0; /*0~1*/
    uint8  dp_id     = 0; /*0~1*/
    uint8  p_core    = 0;
    uint8  is_eunit  = FALSE;
    uint8  core_num  = 1;
    uint16 chan_id   = 0;
    //uint16 dport     = 0;
    uint32 mlen_max  = 0;
    uint32 mlen_min  = 0;
    uint32 dma_en    = 0;
    uint32 dma_chan  = 0;
    uint32 oam_en    = 0;
    uint32 max_net   = 0;
    uint32 mtype     = 0;
    uint32 mout_sel  = 0;
    uint32 mcrdt_thd = 0;
    uint32 hdr       = 0;
    uint32 rm_hdr_en = 0;
    uint32 sub_chan  = 0;
    uint32 cmd       = 0;
    uint32 tbl_id    = 0;
    uint32 index     = 0;
    uint32 value     = 0;
    sys_dmps_db_upt_info_t   port_info = {0};
    BufStoreProcMiscChanIdCfg_m bs_misc_chan;
    DsChannelizeMode_m          ds_mode;
    NetRxMiscCtl_m              netrx_misc_ctl;
    EpeScheduleMiscCtl_m        epe_misc_ctl;
    EpeScheduleCreditCtl_m      epe_credit_ctl;
    QMgrDeqChanIdCfg_m          qmgr_chan_cfg;
    NetRxCtl_m                  netrx_ctl;
    BufStoreDataPrepDpCtl_m     bs_dp_ctl;
    IpeHeaderAdjustChannelPortMap_m ipe_chan_port_map;
    EpeHeaderAdjustChannelPortMap_m epe_chan_port_map;
    DsEpeHeaderEditChannelPortMap_m ds_epe_chan_port_map;

    core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

    for (chan_id = SYS_AT_CHAN_CPUMAC_NETWORK_START; chan_id < SYS_AT_MAX_CHAN_NUM; chan_id++)
    {
        is_eunit  = FALSE;
        if (((chan_id >= SYS_AT_CHAN_CPUMAC_NETWORK_START) && (chan_id <= SYS_AT_CHAN_CPUMAC_NETWORK_END)) ||
            ((chan_id >= SYS_AT_CHAN_CPUMAC_START) && (chan_id <= SYS_AT_CHAN_CPUMAC_END)))
        {
            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_PP_ID);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_DP_ID);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SUB_CHAN_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,     core_id);
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_PP_ID,       pp_id);
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_DP_ID,       dp_id);
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID, sub_chan);
            if (1 == dp_id)
            {
                port_type = ((chan_id >= SYS_AT_CHAN_CPUMAC_NETWORK_START) && (chan_id <= SYS_AT_CHAN_CPUMAC_NETWORK_END)) ?
                    SYS_DMPS_CPUMAC_NETWORK_PORT : SYS_DMPS_CPU_MAC_PORT;
            }
            else
            {
                continue;
            }
        }
        else
        {
            SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id));
            /*SYS_CONDITION_CONTINUE(CTC_E_NONE != sys_usw_dmps_db_get_single_relative_id(lchip,
                DMPS_DB_TYPE_CHAN, chan_id, DMPS_DB_TYPE_PORT, &dport));*/

            CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
            DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID, chan_id);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_PP_ID);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_DP_ID);
            DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SUB_CHAN_ID);
            CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,        port_type);
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,     core_id);
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_PP_ID,       pp_id);
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_DP_ID,       dp_id);
            DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID, sub_chan);
        }

        if ((SYS_DMPS_MAX_PORT_TYPE == port_type) && ((MCHIP_CAP(SYS_CAP_CHANID_EUNIT0) == chan_id) || ((MCHIP_CAP(SYS_CAP_CHANID_EUNIT0) + 1) == chan_id)))
        {
            port_type = SYS_DMPS_DMA_PORT;
            is_eunit  = TRUE;
        }

        SYS_CONDITION_CONTINUE((SYS_DMPS_OAM_PORT != port_type) && (SYS_DMPS_DMA_PORT != port_type) &&
            (SYS_DMPS_ILOOP_PORT != port_type) && (SYS_DMPS_ELOOP_PORT != port_type) &&
            (SYS_DMPS_CPUMAC_NETWORK_PORT != port_type) && (SYS_DMPS_CPU_MAC_PORT != port_type));

        mlen_max  = 16383;
        mlen_min  = 33;

        /*DsChannelizeMode.portMaxLen                 ALL misc in ALL dp  16383                             */
        /*DsChannelizeMode.portMinLen                 ALL misc in ALL dp  33                                */
        tbl_id = DsChannelizeMode_t;
        index = DRV_INS(0, sub_chan);
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &ds_mode));
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, sub_chan, DsChannelizeMode_portMaxLen_f, &mlen_max, &ds_mode);
        DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, sub_chan, DsChannelizeMode_portMinLen_f, &mlen_min, &ds_mode);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &ds_mode));

        if (SYS_DMPS_MISC_SUB_CHAN == sub_chan)
        {
            max_net   = (SYS_DMPS_CPUMAC_NETWORK_PORT == port_type) ? 24 : 23;
            hdr       = (SYS_DMPS_CPUMAC_NETWORK_PORT == port_type) ? 0 : 1;
            rm_hdr_en = (SYS_DMPS_CPUMAC_NETWORK_PORT == port_type) ? 0 : 1;
            dma_en    = (SYS_DMPS_DMA_PORT == port_type) ? (is_eunit ? 0 : 1) : 0;
            dma_chan  = ((SYS_DMPS_DMA_PORT == port_type) || (SYS_DMPS_OAM_PORT == port_type)) ? sub_chan : DMPS_INVALID_VALUE_U16;
            oam_en    = (SYS_DMPS_OAM_PORT == port_type) ? 1 : 0;
            mtype     = (SYS_DMPS_OAM_PORT == port_type) ? 0  : ((SYS_DMPS_DMA_PORT == port_type) ? 1  : 2);
            mout_sel  = (SYS_DMPS_OAM_PORT == port_type) ? 0  : ((SYS_DMPS_DMA_PORT == port_type) ? 1  : 2);
            mcrdt_thd = (SYS_DMPS_OAM_PORT == port_type) ? 80 : ((SYS_DMPS_DMA_PORT == port_type) ? 64 : 128);

            if (0 == dp_id)
            {
                /*QMgrDeqChanIdCfg.cfgDmaChanEn               Get DB (write PEER) SYS_DMPS_DMA_PORT-1  other-0      */
                /*QMgrDeqChanIdCfg.dmaExtEn                   Get DB (write PEER) SYS_DMPS_DMA_PORT-1  other-0      */
                /*QMgrDeqChanIdCfg.cfgDmaChanId               Get DB (write PEER) sub_chan_id SYS_DMPS_MISC_SUB_CHAN*/
                tbl_id = QMgrDeqChanIdCfg_t;
                index = DRV_INS(0, 0);
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &qmgr_chan_cfg));
                DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, tbl_id, 0, 0, QMgrDeqChanIdCfg_cfgDmaChanEn_f, &dma_en,   &qmgr_chan_cfg);
                DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, tbl_id, 0, 0, QMgrDeqChanIdCfg_dmaExtEn_f,     &dma_en,   &qmgr_chan_cfg);
                DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, tbl_id, 0, 0, QMgrDeqChanIdCfg_cfgDmaChanId_f, &dma_chan, &qmgr_chan_cfg);
                cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &qmgr_chan_cfg));

                if (SYS_AT_CHIP_IS_DC(lchip))
                {
                    p_core = (0 == core_id) ? 1 : 0;
                    index = DRV_INS(1, 0);
                    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, p_core, pp_id, cmd, &qmgr_chan_cfg));
                    DRV_IOW_ENTRY_NZ(p_core, pp_id, 0xff, lchip, tbl_id, 1, 0, QMgrDeqChanIdCfg_cfgDmaChanEn_f, &dma_en,   &qmgr_chan_cfg);
                    DRV_IOW_ENTRY_NZ(p_core, pp_id, 0xff, lchip, tbl_id, 1, 0, QMgrDeqChanIdCfg_dmaExtEn_f,     &dma_en,   &qmgr_chan_cfg);
                    DRV_IOW_ENTRY_NZ(p_core, pp_id, 0xff, lchip, tbl_id, 1, 0, QMgrDeqChanIdCfg_cfgDmaChanId_f, &dma_chan, &qmgr_chan_cfg);
                    cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, p_core, pp_id, cmd, &qmgr_chan_cfg));
                }
            }

            if ((SYS_DMPS_CPUMAC_NETWORK_PORT == port_type) || (SYS_DMPS_CPU_MAC_PORT == port_type))
            {
                /*NetRxCtl.cfgMiscPacketHasBrgHdr             Get DB              SYS_DMPS_CPUMAC_NETWORK_PORT-0 other-1  */
                /*NetRxCtl.cfgMiscRemoveCpuHdrEn              Get DB              SYS_DMPS_CPUMAC_NETWORK_PORT-0 other-1  */
                tbl_id = NetRxCtl_t;
                index = DRV_INS(0, 0);
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &netrx_ctl));
                DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, 0, NetRxCtl_cfgMiscPacketHasBrgHdr_f, &hdr,       &netrx_ctl);
                DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, 0, NetRxCtl_cfgMiscRemoveCpuHdrEn_f,  &rm_hdr_en, &netrx_ctl);
                cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &netrx_ctl));
            }

            /*BufStoreDataPrepDpCtl.cfgMaxNetChanId   Get DB              SYS_DMPS_CPUMAC_NETWORK_PORT-24 other-23 */
            tbl_id = BufStoreDataPrepDpCtl_t;
            index = DRV_INS(0, 0);
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &bs_dp_ctl));
            DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, 0, BufStoreDataPrepDpCtl_cfgMaxNetChanId_f,   &max_net,  &bs_dp_ctl);
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &bs_dp_ctl));

            /*BufStoreProcMiscChanIdCfg.cfgDmaChanIdEn    Get DB              SYS_DMPS_DMA_PORT-1  other-0      */
            /*BufStoreProcMiscChanIdCfg.cfgOamOrDmaChanId Get DB              sub_chan_id SYS_DMPS_MISC_SUB_CHAN*/
            /*BufStoreProcMiscChanIdCfg.cfgOamChanIdEn    Get DB              SYS_DMPS_OAM_PORT-1  other-0      */
            /*BufStoreProcMiscChanIdCfg.cfgMaxNetChanId   Get DB              SYS_DMPS_CPUMAC_NETWORK_PORT-24 other-23 */
            tbl_id = BufStoreProcMiscChanIdCfg_t;
            index = DRV_INS(0, 0);
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &bs_misc_chan));
            DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, 0, BufStoreProcMiscChanIdCfg_cfgDmaChanIdEn_f,    &dma_en,   &bs_misc_chan);
            DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, 0, BufStoreProcMiscChanIdCfg_cfgOamOrDmaChanId_f, &dma_chan, &bs_misc_chan);
            DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, 0, BufStoreProcMiscChanIdCfg_cfgOamChanIdEn_f,    &oam_en,   &bs_misc_chan);
            DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, 0, BufStoreProcMiscChanIdCfg_cfgMaxNetChanId_f,   &max_net,  &bs_misc_chan);
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &bs_misc_chan));

            /*NetRxMiscCtl.cfgMiscType                    Get DB              OAM-0, DMA-1, CPUMAC-2            */
            tbl_id = NetRxMiscCtl_t;
            index = DRV_INS(0, 0);
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &netrx_misc_ctl));
            DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, 0, NetRxMiscCtl_cfgMiscType_f, &mtype, &netrx_misc_ctl);
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &netrx_misc_ctl));

            /*EpeScheduleMiscCtl.cfgMiscOutIntfSel        Get DB              OAM-0, DMA-1, CPUMAC-2            */
            tbl_id = EpeScheduleMiscCtl_t;
            index = DRV_INS(0, 0);
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &epe_misc_ctl));
            DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, 0, EpeScheduleMiscCtl_cfgMiscOutIntfSel_f, &mout_sel, &epe_misc_ctl);
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &epe_misc_ctl));

            /*EpeScheduleCreditCtl.toMiscCreditThrd       Get DB              OAM-80, DMA-64, CPUMAC-128        */
            tbl_id = EpeScheduleCreditCtl_t;
            index = DRV_INS(0, 0);
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &epe_credit_ctl));
            DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, tbl_id, 0, 0, EpeScheduleCreditCtl_toMiscCreditThrd_f, &mcrdt_thd, &epe_credit_ctl);
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &epe_credit_ctl));
        }
    }

    /* special config */
    for (core_id = 0; core_id < core_num; core_id++)
    {
        for (pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));
            if (1 == (pp_id % SYS_CORE_PP_NUM(lchip)) || 2 == (pp_id % SYS_CORE_PP_NUM(lchip)))
            {
                tbl_id = IpeHeaderAdjustChannelPortMap_t;
                index = DRV_INS(0, SYS_AT_MISC_CHAN_ID_IN_DP);
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &ipe_chan_port_map));
                value = 0x1E6;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, tbl_id, 0, SYS_AT_MISC_CHAN_ID_IN_DP,
                    IpeHeaderAdjustChannelPortMap_g_0_ppSrcPort_f, &value, &ipe_chan_port_map);
                cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &ipe_chan_port_map));

                tbl_id = EpeHeaderAdjustChannelPortMap_t;
                index = DRV_INS(0, SYS_AT_MISC_CHAN_ID_IN_DP);
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &epe_chan_port_map));
                value = 0x1E6;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, tbl_id, 0, SYS_AT_MISC_CHAN_ID_IN_DP,
                    EpeHeaderAdjustChannelPortMap_g_0_ppDestPort_f, &value, &epe_chan_port_map);
                cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &epe_chan_port_map));

                tbl_id = DsEpeHeaderEditChannelPortMap_t;
                index = DRV_INS(0, SYS_AT_MISC_CHAN_ID_IN_DP);
                cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &ds_epe_chan_port_map));
                value = 0x1E6;
                DRV_IOW_ENTRY_NZ(core_id, pp_id, 0xff, lchip, tbl_id, 0, SYS_AT_MISC_CHAN_ID_IN_DP,
                    DsEpeHeaderEditChannelPortMap_g_0_ppDestPort_f, &value, &ds_epe_chan_port_map);
                cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DMPS_DRV_IOCTL_PP(lchip, index, core_id, pp_id, cmd, &ds_epe_chan_port_map));
            }
        }
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_at_datapath_init_dp(uint8 lchip, ctc_datapath_global_cfg_t* p_dp_cfg)
{
    uint8  core_id      = 0;
    uint8  core_num     = 1;
    uint8  dp_id        = 0;
    uint8  pp_id        = 0;
#ifndef PCS_ONLY
    uint8  dp_txqm_id   = 0;
    uint16 dport        = 0;
    uint16 chan_id      = 0;
    sys_dmps_change_chan_info_t info = {0};
#endif

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    /* get core_num by sdk api or chip sub type */
    core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

#ifdef PCS_ONLY
    for (core_id = 0; core_id < core_num; core_id++)
    {
        for (pp_id = 0; pp_id < 2; pp_id++)
        {
            for (dp_id = 0; dp_id < AT_DP_NUM_PER_PP; dp_id++)
            {
                CTC_ERROR_RETURN(_sys_at_datapath_nettx_init(lchip, core_id, pp_id, dp_id));
                CTC_ERROR_RETURN(_sys_at_datapath_netrx_init(lchip, core_id, pp_id, dp_id));
            }
        }
    }
#else
    CTC_ERROR_RETURN(_sys_at_datapath_map_pre(lchip));

    for (dport = 0; dport < SYS_USW_MAX_PORT_NUM_PER_CHIP; dport++)
    {
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PORT, dport));
        SYS_CONDITION_CONTINUE(sys_usw_dmps_db_get_dport_relative_id(lchip, dport, DMPS_DB_TYPE_CHAN, &chan_id));

        /* dport/chan map by dport */
        CTC_ERROR_RETURN(_sys_at_datapath_map_by_port(lchip, dport, chan_id, CHAN_DIR_TXRX));
    }

    for (chan_id = 0; chan_id < SYS_USW_MAX_PORT_NUM_PER_CHIP; chan_id++)
    {
        SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_CHAN, chan_id));
        if (CTC_E_NONE != sys_usw_dmps_db_get_relative_id(lchip, DMPS_DB_TYPE_CHAN, chan_id, DMPS_DB_TYPE_PORT, NULL, &dport))
        {
            dport = DMPS_INVALID_VALUE_U16;
        }

        /* dport/chan/sub_chan map by chan */
        CTC_ERROR_RETURN(_sys_at_datapath_map_by_chan(lchip, dport, chan_id, CHAN_DIR_TXRX));
    }

    CTC_ERROR_RETURN(_sys_at_datapath_init_chan_type(lchip));

    for (core_id = 0; core_id < core_num; core_id++)
    {
        for (pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));
            for (dp_id = 0; dp_id < AT_DP_NUM_PER_PP; dp_id++)
            {
                /* check bw, credit and calendar */
                for(dp_txqm_id = 0; dp_txqm_id < SYS_AT_TXQM_NUM_PER_DP; dp_txqm_id++)
                {
                    CTC_ERROR_RETURN(_sys_at_datapath_check(lchip, core_id, pp_id, dp_id, dp_txqm_id, &info, CHAN_DIR_TXRX, TRUE));
                }

                CTC_ERROR_RETURN(_sys_at_datapath_set_extra_cfg(lchip, core_id, pp_id, dp_id));

                /*set Epe, NetRx, BufRetrv calendar*/
                CTC_ERROR_RETURN(_sys_at_datapath_set_general_calendar(lchip, core_id, pp_id, dp_id, CHAN_DIR_TXRX));

                /*set nettx calendar*/
                for(dp_txqm_id = 0; dp_txqm_id < SYS_AT_TXQM_NUM_PER_DP; dp_txqm_id++)
                {
                    CTC_ERROR_RETURN(_sys_at_datapath_set_nettx_calendar(lchip, core_id, pp_id, dp_id, dp_txqm_id));
                }

                /*netrx: chan-mac mapping, wrr weight*/
                CTC_ERROR_RETURN(_sys_at_datapath_netrx_init(lchip, core_id, pp_id, dp_id));

                /*bufretrv: credit, wrr weight*/
                CTC_ERROR_RETURN(_sys_at_datapath_bufretrv_init(lchip, core_id, pp_id, dp_id));

                /*epe: chan-mac mapping, credit, xglg en, wrr weight*/
                CTC_ERROR_RETURN(_sys_at_datapath_epe_init(lchip, core_id, pp_id, dp_id));

                /*nettx: credit, txthrd, timerEn, ready*/
                CTC_ERROR_RETURN(_sys_at_datapath_nettx_init(lchip, core_id, pp_id, dp_id));
            }

            /*qmgr init, total 2 dp: credit, xglg chan en, weight, start end*/
            CTC_ERROR_RETURN(_sys_at_datapath_qmgr_init(lchip, core_id, pp_id));
        }
    }
#endif

    CTC_ERROR_RETURN(_sys_at_datapath_misc_port_cfg(lchip));

    DP_DEBUG_FUNCTION_RETURN_PRINT();
    return CTC_E_NONE;
}

int32
_sys_at_datapath_init_pulse(uint8 lchip)
{
#if !defined(EMULATION_ENV) && (SDK_WORK_PLATFORM == 0)
    uint8  core_id   = 0;
    uint8  pp_id     = 0;
    uint8  core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;
    uint32 value     = 0;
    uint32 tbl_id    = 0;
    uint32 cmd       = 0;
    RefDivMcMacPulse_m rf_mac;
    RefDivMiscPulse_m  rf_misc;
    RefDivSlice0PPPulse_m rf_pp0;

    for (core_id = 0; core_id < core_num; core_id++)
    {
        tbl_id = RefDivMcMacPulse_t;
        cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &rf_mac));
        value= 0;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMcMacPulse_cfgResetDivMcMacHiBerPulse_f,       &value, &rf_mac);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMcMacPulse_cfgResetDivMcMacLinkFilterPulse_f,  &value, &rf_mac);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMcMacPulse_cfgResetDivMcMacPauseLockPulse_f,   &value, &rf_mac);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMcMacPulse_cfgResetDivMcMacPauseTimer0Pulse_f, &value, &rf_mac);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMcMacPulse_cfgResetDivMcMacPauseTimer1Pulse_f, &value, &rf_mac);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMcMacPulse_cfgResetDivMcMacPauseTimer2Pulse_f, &value, &rf_mac);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMcMacPulse_cfgResetDivMcMacPauseTimer3Pulse_f, &value, &rf_mac);
        cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &rf_mac));

        tbl_id = RefDivMiscPulse_t;
        cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &rf_misc));
        value= 0;
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMiscPulse_cfgResetDivCpuMacHiBerPulse_f,       &value, &rf_misc);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMiscPulse_cfgResetDivCpuMacLinkFilterPulse_f,  &value, &rf_misc);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMiscPulse_cfgResetDivCpuMacLinkPulse_f,        &value, &rf_misc);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMiscPulse_cfgResetDivCpuMacPauseLockPulse_f,   &value, &rf_misc);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMiscPulse_cfgResetDivCpuMacPauseTimer0Pulse_f, &value, &rf_misc);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMiscPulse_cfgResetDivCpuMacPauseTimer1Pulse_f, &value, &rf_misc);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMiscPulse_cfgResetDivCpuMacPauseTimer2Pulse_f, &value, &rf_misc);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivMiscPulse_cfgResetDivCpuMacPauseTimer3Pulse_f, &value, &rf_misc);
        cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &rf_misc));

        for (pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));
            tbl_id = RefDivSlice0PPPulse_t + pp_id * (RefDivSlice1PPPulse_t - RefDivSlice0PPPulse_t);
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &rf_pp0));
            value= 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivSlice0PPPulse_cfgSlice0ResetDivCoppEpeUpdPulse_f,             &value, &rf_pp0);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivSlice0PPPulse_cfgSlice0ResetDivCoppIpeUpdPulse_f,             &value, &rf_pp0);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivSlice0PPPulse_cfgSlice0ResetDivDlbPulse_f,                    &value, &rf_pp0);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivSlice0PPPulse_cfgSlice0ResetDivEfdPulse_f,                    &value, &rf_pp0);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivSlice0PPPulse_cfgSlice0ResetDivEpeHdrEditChanAvgLoadPulse_f,  &value, &rf_pp0);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivSlice0PPPulse_cfgSlice0ResetDivEpePolicing0UpdPulse_f,        &value, &rf_pp0);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivSlice0PPPulse_cfgSlice0ResetDivIpePolicing0UpdPulse_f,        &value, &rf_pp0);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivSlice0PPPulse_cfgSlice0ResetDivEpePolicing1UpdPulse_f,        &value, &rf_pp0);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivSlice0PPPulse_cfgSlice0ResetDivIpePolicing1UpdPulse_f,        &value, &rf_pp0);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivSlice0PPPulse_cfgSlice0ResetDivSvcPolicingUpdPulse_f,         &value, &rf_pp0);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivSlice0PPPulse_cfgSlice0ResetDivQMgrDeqShpPulse_f,             &value, &rf_pp0);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivSlice0PPPulse_cfgSlice0ResetDivStormCtl0UpdPulse_f,           &value, &rf_pp0);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, 0, RefDivSlice0PPPulse_cfgSlice0ResetDivStormCtl1UpdPulse_f,           &value, &rf_pp0);
            cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &rf_pp0));
        }
    }
#endif

    return CTC_E_NONE;
}

int32
sys_at_datapath_check_credit_flush_clear(uint8 lchip, uint32 mac_id, uint32 chan_id)
{
    uint8  core_id           = 0;
    uint8  pp_id             = 0;
    uint8  dp_id             = 0;
    uint8  dp_chan_id        = 0;
    uint8  dp_txqm_id        = 0;
    uint8  mac_client        = 0;
    uint8  txqm_mac_client   = 0;
    uint8  port_type         = 0;
    uint32 cmd               = 0;
    uint32 index             = 0;
    uint32 credit            = 0;
    uint32 cnt               = 0;
    uint32 tbl_id            = 0;
    uint32 step              = NetTxCreditUsed1_t - NetTxCreditUsed0_t;
    NetTxCreditUsed0_m       nettx_credit_used;
    PostBrSopCreditMem_m     br_dp_sop_credit;
    PostBrBodyCreditMem_m    br_dp_body_credit;
    sys_dmps_db_upt_info_t   port_info = {0};

    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_CHAN_ID,                 chan_id);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_CORE_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_PP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_DP_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_TXQM_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_SUB_CHAN_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID);
    DMPS_DB_SET_PROPERTY_UPDATE(port_info, DMPS_DB_PORT_TYPE);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID,       core_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_PP_ID,         pp_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_DP_ID,         dp_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_TXQM_ID,       dp_txqm_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_SUB_CHAN_ID,   dp_chan_id);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_MAC_CLIENT_ID, mac_client);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PORT_TYPE,          port_type);

    txqm_mac_client = mac_client % SYS_AT_MAC_CLIENT_PER_TXQM;

    if (!SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id))
    {
        return CTC_E_NONE;
    }

    /* 1. check BufRetrvDPSopCreditMem.credit*/
    credit = 0;
    cnt    = 0;
    index  = DRV_INS(0, dp_chan_id);
    cmd    = DRV_IOR(PostBrSopCreditMem_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &br_dp_sop_credit));
    DRV_IOR_FIELD(lchip, PostBrSopCreditMem_t, PostBrSopCreditMem_credit_f, &credit, &br_dp_sop_credit);

    while(credit)
    {
#ifdef EMULATION_ENV
        sal_task_sleep(1000);
#else
        sal_task_sleep(20);
#endif
        if((cnt++) > 50)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " BufRetrvDPSopCreditMem_credit (chan: %d) cannot return to Zero \n", 
                chan_id);
            return CTC_E_HW_FAIL;
        }
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &br_dp_sop_credit));
        DRV_IOR_FIELD(lchip, PostBrSopCreditMem_t, PostBrSopCreditMem_credit_f, &credit, &br_dp_sop_credit);
    }

    /* 2. BufRetrvDPBodyCreditMem.credit*/
    credit = 0;
    cnt    = 0;
    index  = DRV_INS(0, dp_chan_id);
    cmd    = DRV_IOR(PostBrBodyCreditMem_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &br_dp_body_credit));
    DRV_IOR_FIELD(lchip, PostBrBodyCreditMem_t, PostBrBodyCreditMem_credit_f, &credit, &br_dp_body_credit);
    while(credit)
    {
#ifdef EMULATION_ENV
        sal_task_sleep(1000);
#else
        sal_task_sleep(20);
#endif
        if((cnt++) > 50)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " BufRetrvDPBodyCreditMem_credit (chan: %d) cannot return to Zero \n", 
                chan_id);
            return CTC_E_HW_FAIL;
        }
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &br_dp_body_credit));
        DRV_IOR_FIELD(lchip, PostBrBodyCreditMem_t, PostBrBodyCreditMem_credit_f, &credit, &br_dp_body_credit);
    }

    SYS_CONDITION_RETURN((SYS_DMPS_NETWORK_PORT != port_type), CTC_E_NONE);

    /* 3. check NetTxCreditUsed0.creditUsed*/
    credit = 0;
    cnt    = 0;
    tbl_id = NetTxCreditUsed0_t + step * dp_txqm_id;
    index  = DRV_INS(0, txqm_mac_client);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &nettx_credit_used));
    DRV_IOR_FIELD(lchip, tbl_id, NetTxCreditUsed0_creditUsed_f, &credit, &nettx_credit_used);
    while(credit)
    {
#ifdef EMULATION_ENV
        sal_task_sleep(1000);
#else
        sal_task_sleep(20);
#endif
        if((cnt++) >50)
        {
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "NetTxCreditUsed%d_creditUsed (chan: %d) cannot return to Zero \n", 
                dp_txqm_id, chan_id);
            return CTC_E_HW_FAIL;
        }
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_DP(lchip, index, core_id, pp_id, dp_id, cmd, &nettx_credit_used));
        DRV_IOR_FIELD(lchip, tbl_id, NetTxCreditUsed0_creditUsed_f, &credit, &nettx_credit_used);
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_check_cfg_param(uint8 lchip, ctc_datapath_global_cfg_t* p_datapath_cfg)
{
    uint8 core_num  = 1;
    uint8 core_id   = 0;
    uint8 cnt       = 0;
    uint8 dual_cnt  = 0;
    uint8 quad_cnt  = 0;
    uint8 octl_cnt  = 0;
    uint8 dual_flag = FALSE;
    uint8 quad_flag = FALSE;
    uint8 octl_flag = FALSE;
    uint8 lane_num  = 0;
    uint8 mac_group_id       = 0;
    uint16 lsd = 0;
    ctc_datapath_serdes_prop_t *p_serdes = p_datapath_cfg->serdes;

    core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

    /* NetWork database init */
    for(core_id = 0; core_id < core_num; core_id++)
    {
        for (mac_group_id = 0; mac_group_id < AT_MCMAC_NUM_PER_CORE; mac_group_id++)
        {
            /* ignore invalid mac_group */
            if (!SYS_AT_MAC_GROUP_IS_VAILD(lchip, core_id, mac_group_id))
            {
                continue;
            }

            for (cnt = 0; cnt < AT_SERDES_NUM_PER_MCMAC; cnt++)
            {
                lsd = cnt + mac_group_id * AT_SERDES_NUM_PER_MCMAC + core_id * AT_SERDES_NUM_PER_CORE;

                if(SYS_AT_IS_MODE_NONE(p_serdes[lsd].mode))
                {
                    p_serdes[lsd].mode = CTC_CHIP_SERDES_NONE_MODE;
                }
                SYS_AT_GET_SERDES_NUM_BY_MODE(p_serdes[lsd].mode, lane_num);

                /*multi-lane mode check*/
                switch(lane_num)
                {
                    case 2:
                        /*invalid condition: current lane is 0 in a multi-lane series (!dual_flag), but no lane count before*/
                        if((0 != dual_cnt) && (!dual_flag))
                        {
                            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " Error 1: serdes logic lane %u mode %u!\n", 
                                lsd, p_serdes[lsd].mode);
                            return CTC_E_INVALID_CONFIG;
                        }
                        /*invalid condition: current lane is 0 in a multi-lane series (0 == dual_cnt), but lane id is wrong*/
                        if((0 == dual_cnt) && (0 != (lsd % 2)))
                        {
                            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " Error 2: Serdes logic lane %u mode %u!\n", 
                                lsd, p_serdes[lsd].mode);
                            return CTC_E_INVALID_CONFIG;
                        }

                        dual_cnt++;
                        dual_flag = TRUE;

                        /*invalid condition: count of multi-lane exceeds max value*/
                        if(2 < dual_cnt)
                        {
                            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " Error 3: Serdes logic lane %u mode %u dual_cnt %u!\n", 
                                lsd, p_serdes[lsd].mode, dual_cnt);
                            return CTC_E_INVALID_CONFIG;
                        }
                        /*if count of multi-lane reaches limit, set dual_flag to false for next multi-lane series*/
                        else if(2 == dual_cnt)
                        {
                            dual_flag = FALSE;
                            dual_cnt = 0;
                        }
                        break;
                    case 4:
                        /*invalid condition: current lane is 0 in a multi-lane series (!dual_flag), but no lane count before*/
                        if((0 != quad_cnt) && (!quad_flag))
                        {
                            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " Error 4: serdes logic lane %u mode %u!\n", 
                                lsd, p_serdes[lsd].mode);
                            return CTC_E_INVALID_CONFIG;
                        }
                        /*invalid condition: current lane is 0 in a multi-lane series (0 == dual_cnt), but lane id is wrong*/
                        if((0 == quad_cnt) && (0 != (lsd % 4)))
                        {
                            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " Error 5: Serdes logic lane %u mode %u!\n", 
                                lsd, p_serdes[lsd].mode);
                            return CTC_E_INVALID_CONFIG;
                        }

                        quad_cnt++;
                        quad_flag = TRUE;

                        /*invalid condition: count of multi-lane exceeds max value*/
                        if(4 < quad_cnt)
                        {
                            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " Error 6: Serdes logic lane %u mode %u dual_cnt %u!\n", 
                                lsd, p_serdes[lsd].mode, dual_cnt);
                            return CTC_E_INVALID_CONFIG;
                        }
                        /*if count of multi-lane reaches limit, set dual_flag to false for next multi-lane series*/
                        else if(4 == quad_cnt)
                        {
                            quad_flag = FALSE;
                            quad_cnt = 0;
                        }
                        break;
                    case 8:
                        /*invalid condition: current lane is 0 in a multi-lane series (!dual_flag), but no lane count before*/
                        if((0 != octl_cnt) && (!octl_flag))
                        {
                            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " Error 7: serdes logic lane %u mode %u!\n", 
                                lsd, p_serdes[lsd].mode);
                            return CTC_E_INVALID_CONFIG;
                        }
                        /*invalid condition: current lane is 0 in a multi-lane series (0 == dual_cnt), but lane id is wrong*/
                        if((0 == octl_cnt) && (0 != (lsd % 8)))
                        {
                            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " Error 8: Serdes logic lane %u mode %u!\n", 
                                lsd, p_serdes[lsd].mode);
                            return CTC_E_INVALID_CONFIG;
                        }

                        octl_cnt++;
                        octl_flag = TRUE;

                        /*invalid condition: count of multi-lane exceeds max value*/
                        if(8 < octl_cnt)
                        {
                            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " Error 9: Serdes logic lane %u mode %u dual_cnt %u!\n", 
                                lsd, p_serdes[lsd].mode, dual_cnt);
                            return CTC_E_INVALID_CONFIG;
                        }
                        /*if count of multi-lane reaches limit, set dual_flag to false for next multi-lane series*/
                        else if(8 == octl_cnt)
                        {
                            octl_flag = FALSE;
                            octl_cnt = 0;
                        }
                        break;
                    case 1:
                    default:
                        dual_cnt = 0;
                        quad_cnt = 0;
                        octl_cnt = 0;
                        break;
                }
            }
        }
    }

    return CTC_E_NONE;
}

int32
datapath_print(uint8 lchip, ctc_datapath_global_cfg_t* p_datapath_cfg)
{
    uint16 i;
    sal_printf("****************************************************************************************\n");
    sal_printf("Core Freq A: %u\nCore Freq B: %u\nWLAN enable: %u\nDot1AE enable: %u\nDatapath type: %u\nFlexE channel: %u %u\n", 
        p_datapath_cfg->core_frequency_a, p_datapath_cfg->core_frequency_b, 
        p_datapath_cfg->wlan_enable, p_datapath_cfg->dot1ae_enable, 0, 
        p_datapath_cfg->flexe_client_num[0], p_datapath_cfg->flexe_client_num[1]);
    sal_printf("****************************************************************************************\n");
    sal_printf("index  logic  mode  is_dynamic  rx_polarity  tx_polarity  is_xpipe  serdes_id\n");
    for(i = 0; i < MCHIP_CAP(SYS_CAP_DMPS_SERDES_NUM_PER_SLICE); i++)
    {
        
        sal_printf("%5u  %5u  %4u  %10u  %11u  %11u  %8u  %9u\n",
            i, p_datapath_cfg->serdes[i].logical_serdes_id, p_datapath_cfg->serdes[i].mode, p_datapath_cfg->serdes[i].is_dynamic, 
            p_datapath_cfg->serdes[i].rx_polarity, p_datapath_cfg->serdes[i].tx_polarity, p_datapath_cfg->serdes[i].is_xpipe, 
            p_datapath_cfg->serdes[i].physical_serdes_id);
    }
    sal_printf("****************************************************************************************\n");

    return CTC_E_NONE;
}

int32
_sys_at_datapath_power_down_dp(uint8 lchip)
{
    /*uint8  core_id   = 0;
    uint8  pp_id     = 0;
    uint8  dp_id     = 0;
    uint8  g_dp_id   = 0;
    uint8  core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;
    uint32 step      = 0;
    uint32 fld_id    = 0;*/
    CtcBufStoreProcTopCtlModuleEnable_m bs_module_en;
    CtcPreBrCtlModuleEnable_m           br_module_en;
    CtcQMgrEnqModuleEnable_m            qmgr_module_en;

    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "### %s enter\n", __FUNCTION__);
    DP_DEBUG_FUNCTION_CALLED_PRINT(); 
#if 0
    for (core_id = 0; core_id < core_num; core_id++)
    {
        for (pp_id = 0; pp_id < AT_PP_NUM_PER_CORE; pp_id++)
        {
            SYS_CONDITION_CONTINUE(SYS_AT_PP_IS_VAILD(lchip, core_id, pp_id));

            step    = CtcQMgrEnqModuleEnable_enClkQMgrQWriteSlice1_f -
                        CtcQMgrEnqModuleEnable_enClkQMgrQWriteSlice0_f;
            fld_id  = CtcQMgrEnqModuleEnable_enClkQMgrQWriteSlice0_f + pp_id * step;
            CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                CtcQMgrEnqModuleEnable_t, fld_id, 0, 0, &qmgr_module_en));

            step    = CtcQMgrEnqModuleEnable_enClkQMgrSubLocalSlice1_f -
                        CtcQMgrEnqModuleEnable_enClkQMgrSubLocalSlice0_f;
            fld_id  = CtcQMgrEnqModuleEnable_enClkQMgrSubLocalSlice0_f + pp_id * step;
            CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                CtcQMgrEnqModuleEnable_t, fld_id, 0, 0, &qmgr_module_en));

            step    = CtcQMgrEnqModuleEnable_enClkQMgrSchSlice1_f -
                        CtcQMgrEnqModuleEnable_enClkQMgrSchSlice0_f;
            fld_id  = CtcQMgrEnqModuleEnable_enClkQMgrSchSlice0_f + pp_id * step;
            CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                CtcQMgrEnqModuleEnable_t, fld_id, 0, 0, &qmgr_module_en));

            if (SYS_AT_CHIP_IS_DC(lchip))
            {
                step    = CtcQMgrEnqModuleEnable_enClkQMgrSubRemoteSlice1_f -
                            CtcQMgrEnqModuleEnable_enClkQMgrSubRemoteSlice0_f;
                fld_id  = CtcQMgrEnqModuleEnable_enClkQMgrSubRemoteSlice0_f + pp_id * step;
                CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 1 - core_id,
                    CtcQMgrEnqModuleEnable_t, fld_id, 0, 0, &qmgr_module_en));
            }

            for (dp_id = 0; dp_id < AT_DP_NUM_PER_PP; dp_id++)
            {
                g_dp_id = dp_id + AT_DP_NUM_PER_PP * (pp_id + core_id * AT_PP_NUM_PER_CORE);

                step    = CtcBufStoreProcTopCtlModuleEnable_enClkBufStoreErmDp1_f -
                            CtcBufStoreProcTopCtlModuleEnable_enClkBufStoreErmDp0_f;
                fld_id  = CtcBufStoreProcTopCtlModuleEnable_enClkBufStoreErmDp0_f + g_dp_id * step;
                CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                    CtcBufStoreProcTopCtlModuleEnable_t, fld_id, 0, 0, &bs_module_en));

                step    = CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp1EB_f -
                            CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp0EB_f;
                fld_id  = CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp0EB_f + g_dp_id * step;
                CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                    CtcPreBrCtlModuleEnable_t, fld_id, 0, 0, &br_module_en));

                step    = CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp1PbIntf_f -
                            CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp0PbIntf_f;
                fld_id  = CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp0PbIntf_f + g_dp_id * step;
                CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                    CtcPreBrCtlModuleEnable_t, fld_id, 0, 0, &br_module_en));

                step    = CtcPreBrCtlModuleEnable_enClkBufRetrvPreBrDp1_f -
                            CtcPreBrCtlModuleEnable_enClkBufRetrvPreBrDp0_f;
                fld_id  = CtcPreBrCtlModuleEnable_enClkBufRetrvPreBrDp0_f + g_dp_id * step;
                CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                    CtcPreBrCtlModuleEnable_t, fld_id, 0, 0, &br_module_en));

                if (SYS_AT_CHIP_IS_DC(lchip))
                {
                    step    = CtcBufStoreProcTopCtlModuleEnable_enClkBufStoreErmDp1_f -
                                CtcBufStoreProcTopCtlModuleEnable_enClkBufStoreErmDp0_f;
                    fld_id  = CtcBufStoreProcTopCtlModuleEnable_enClkBufStoreErmDp0_f + g_dp_id * step;
                    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 1 - core_id,
                        CtcBufStoreProcTopCtlModuleEnable_t, fld_id, 0, 0, &bs_module_en));

                    step    = CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp1PbIntf_f -
                                CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp0PbIntf_f;
                    fld_id  = CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp0PbIntf_f + g_dp_id * step;
                    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 1 - core_id,
                        CtcPreBrCtlModuleEnable_t, fld_id, 0, 0, &br_module_en));

                    step    = CtcPreBrCtlModuleEnable_enClkBufRetrvPreBrDp1_f -
                                CtcPreBrCtlModuleEnable_enClkBufRetrvPreBrDp0_f;
                    fld_id  = CtcPreBrCtlModuleEnable_enClkBufRetrvPreBrDp0_f + g_dp_id * step;
                    CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 1 - core_id,
                        CtcPreBrCtlModuleEnable_t, fld_id, 0, 0, &br_module_en));
                }
            }
        }
    }
#endif
    /* close remote dp */
    if (!SYS_AT_CHIP_IS_DC(lchip))
    {
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcQMgrEnqModuleEnable_t, CtcQMgrEnqModuleEnable_enClkQMgrSubRemoteSlice0_f, 0, 0, &qmgr_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcQMgrEnqModuleEnable_t, CtcQMgrEnqModuleEnable_enClkQMgrSubRemoteSlice1_f, 0, 0, &qmgr_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcQMgrEnqModuleEnable_t, CtcQMgrEnqModuleEnable_enClkQMgrSubRemoteSlice2_f, 0, 0, &qmgr_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcQMgrEnqModuleEnable_t, CtcQMgrEnqModuleEnable_enClkQMgrSubRemoteSlice3_f, 0, 0, &qmgr_module_en));

        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcBufStoreProcTopCtlModuleEnable_t, CtcBufStoreProcTopCtlModuleEnable_enClkBufStoreErmDp8_f, 0, 0, &bs_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcBufStoreProcTopCtlModuleEnable_t, CtcBufStoreProcTopCtlModuleEnable_enClkBufStoreErmDp9_f, 0, 0, &bs_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcBufStoreProcTopCtlModuleEnable_t, CtcBufStoreProcTopCtlModuleEnable_enClkBufStoreErmDp10_f, 0, 0, &bs_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcBufStoreProcTopCtlModuleEnable_t, CtcBufStoreProcTopCtlModuleEnable_enClkBufStoreErmDp11_f, 0, 0, &bs_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcBufStoreProcTopCtlModuleEnable_t, CtcBufStoreProcTopCtlModuleEnable_enClkBufStoreErmDp12_f, 0, 0, &bs_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcBufStoreProcTopCtlModuleEnable_t, CtcBufStoreProcTopCtlModuleEnable_enClkBufStoreErmDp13_f, 0, 0, &bs_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcBufStoreProcTopCtlModuleEnable_t, CtcBufStoreProcTopCtlModuleEnable_enClkBufStoreErmDp14_f, 0, 0, &bs_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcBufStoreProcTopCtlModuleEnable_t, CtcBufStoreProcTopCtlModuleEnable_enClkBufStoreErmDp15_f, 0, 0, &bs_module_en));

        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp8PbIntf_f, 0, 0, &br_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp9PbIntf_f, 0, 0, &br_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp10PbIntf_f, 0, 0, &br_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp11PbIntf_f, 0, 0, &br_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp12PbIntf_f, 0, 0, &br_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp13PbIntf_f, 0, 0, &br_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp14PbIntf_f, 0, 0, &br_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPostBrDp15PbIntf_f, 0, 0, &br_module_en));

        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPreBrDp8_f, 0, 0, &br_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPreBrDp9_f, 0, 0, &br_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPreBrDp10_f, 0, 0, &br_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPreBrDp11_f, 0, 0, &br_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPreBrDp12_f, 0, 0, &br_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPreBrDp13_f, 0, 0, &br_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPreBrDp14_f, 0, 0, &br_module_en));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, 0,
            CtcPreBrCtlModuleEnable_t, CtcPreBrCtlModuleEnable_enClkBufRetrvPreBrDp15_f, 0, 0, &br_module_en));
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_check_serdes_scale(uint8 lchip, ctc_datapath_global_cfg_t* p_cfg)
{
    uint8 mode = p_cfg->mode;

    if (DRV_CHIP_SUB_TYPE_1 == SYS_AT_GET_CHIP_TYPE(lchip))
    {
        if (0 == mode)
        {
            if (4 != SYS_PP_NUM(lchip))
            {
                SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " %% MODE is not matched with pp_num!\n");
                return CTC_E_INVALID_CONFIG;
            }
            else
            {
                (void) sys_usw_dmps_db_set_serdes_scale(lchip, (uint8) SYS_DMPS_DB_SERDES_SCALE_0);
            }
        }
        else if (1 == mode)
        {
            if (4 != SYS_PP_NUM(lchip))
            {
                SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " %% MODE is not matched with pp_num!\n");
                return CTC_E_INVALID_CONFIG;
            }
            else
            {
                (void) sys_usw_dmps_db_set_serdes_scale(lchip, (uint8) SYS_DMPS_DB_SERDES_SCALE_1);
            }
        }
        else if (2 == mode)
        {
            if (3 != SYS_PP_NUM(lchip))
            {
                SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " %% MODE is not matched with pp_num!\n");
                return CTC_E_INVALID_CONFIG;
            }
            else
            {
                (void) sys_usw_dmps_db_set_serdes_scale(lchip, (uint8) SYS_DMPS_DB_SERDES_SCALE_2);
            }
        }
        else if (3 == mode)
        {
            if (4 != SYS_PP_NUM(lchip))
            {
                SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " %% MODE is not matched with pp_num!\n");
                return CTC_E_INVALID_CONFIG;
            }
            else
            {
                (void) sys_usw_dmps_db_set_serdes_scale(lchip, (uint8) SYS_DMPS_DB_SERDES_SCALE_3);
            }
        }
    }
    else if (DRV_CHIP_SUB_TYPE_3 == SYS_AT_GET_CHIP_TYPE(lchip))
    {
        if (0 == mode)
        {
            if (8 != SYS_PP_NUM(lchip))
            {
                SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " %% MODE is not matched with pp_num!\n");
                return CTC_E_INVALID_CONFIG;
            }
            else
            {
                (void) sys_usw_dmps_db_set_serdes_scale(lchip, (uint8) SYS_DMPS_DB_SERDES_SCALE_4);
            }
        }
        else if (1 == mode)
        {
            if (6 != SYS_PP_NUM(lchip))
            {
                SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " %% MODE is not matched with pp_num!\n");
                return CTC_E_INVALID_CONFIG;
            }
            else
            {
                (void) sys_usw_dmps_db_set_serdes_scale(lchip, (uint8) SYS_DMPS_DB_SERDES_SCALE_5);
            }
        }
    }

    return CTC_E_NONE;
}

int32
sys_at_datapath_init_rsv_port(uint8 lchip)
{
    uint16 index = 0;
    uint16 cnt = 0;
    sys_internal_port_info_t port_info = {0};

    /*init all rsv port db (moved from internal port init)*/
    for (index = SYS_INTERNAL_PORT_START; index <= SYS_INTERNAL_PORT_END; index++)
    {
        port_info.lport       = index;
        port_info.chan_id     = SYS_DMPS_INVALID_CHAN_ID;
        port_info.pp_id       = SYS_DMPS_INVALID_U8;
        port_info.dp_id       = SYS_DMPS_INVALID_U8;
        port_info.sub_chan_id = SYS_DMPS_INVALID_SUB_CHAN_ID;
        port_info.speed_mode  = SYS_PORT_SPEED_MAX;
        port_info.port_type   = SYS_DMPS_RSV_PORT;
        CTC_ERROR_RETURN(sys_usw_dmps_db_set_internal_port_info(lchip, &port_info));
        (void)sys_usw_dmps_db_assign_port(lchip, port_info.lport);
    }

    if (SYS_INTERNAL_PORT_START > SYS_SPECIAL_RSV_PORT_START)
    {
        cnt = SYS_INTERNAL_PORT_START - SYS_SPECIAL_RSV_PORT_START;
        cnt = (cnt <= 4) ? cnt : 4;
        for (index = 0; index < cnt; index++)
        {
            port_info.lport       = index + SYS_SPECIAL_RSV_PORT_START;
            port_info.chan_id     = SYS_DMPS_INVALID_CHAN_ID;
            port_info.pp_id       = SYS_DMPS_INVALID_U8;
            port_info.dp_id       = SYS_DMPS_INVALID_U8;
            port_info.sub_chan_id = SYS_DMPS_INVALID_SUB_CHAN_ID;
            port_info.speed_mode  = SYS_PORT_SPEED_MAX;
            port_info.port_type   = SYS_DMPS_RSV_PORT;
            CTC_ERROR_RETURN(sys_usw_dmps_db_set_internal_port_info(lchip, &port_info));
            (void)sys_usw_dmps_db_assign_port(lchip, port_info.lport);
        }
    }
    return CTC_E_NONE;
}

int32
sys_at_datapath_init_db(uint8 lchip, void* p_glb_cfg)
{
    uint8  bpe_full_mode = 0;
    ctc_datapath_global_cfg_t* p_dp_cfg = (ctc_datapath_global_cfg_t*)p_glb_cfg;

    SYS_CONDITION_RETURN(!p_dp_cfg, CTC_E_INVALID_PTR);

    /*datapath_cfg.txt param check*/
    CTC_ERROR_RETURN(_sys_at_datapath_check_cfg_param(lchip, p_dp_cfg));

    /* check mode when chip_type is 9260 or 9280 */
    CTC_ERROR_RETURN(_sys_at_datapath_check_serdes_scale(lchip, p_dp_cfg));

    CTC_ERROR_RETURN(sys_usw_dmps_db_set_core_pll(lchip, p_dp_cfg->core_frequency_a));

    /*init bpe full mode*/
    bpe_full_mode = p_dp_cfg->bpe_full_mode;
    CTC_ERROR_RETURN(sys_usw_dmps_db_set_bpe_full_mode(lchip, bpe_full_mode));
    
    if ((!CTC_WB_ENABLE(lchip)) || (CTC_WB_STATUS(lchip) != CTC_WB_STATUS_RELOADING))
    {
        /*mac group init */
        CTC_ERROR_RETURN(_sys_at_datapath_init_mac_group(lchip));

        CTC_ERROR_RETURN(_sys_at_datapath_init_chan_2_logic_serdes_map(lchip, p_dp_cfg));
        CTC_ERROR_RETURN(_sys_at_datapath_init_mapping(lchip, p_dp_cfg));

#ifdef AT_CPUMAC
        CTC_ERROR_RETURN(_sys_at_datapath_init_cpumac_mapping(lchip, p_dp_cfg));
#endif

        CTC_ERROR_RETURN(sys_at_datapath_init_rsv_port(lchip));
    }

    if(bpe_full_mode)
    {
        SYS_INTERNAL_PORT_START = 0;
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_check_core_pll_lock(uint8 lchip, uint8 core_id)
{
    uint32 value = 0;
    PllCoreDpMon_m core_dp_mon;
    PllCorePpMon_m core_pp_mon;
    PllTsMon_m     ts_mon;
    
    /* check PLL lock */
    CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
        PllCoreDpMon_t, PllCoreDpMon_monPllCoreDpPllLock_f, 0, &value, &core_dp_mon));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [DATAPATH] core %d pll dp cannot lock \n", core_id);
        return CTC_E_HW_NOT_LOCK;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
        PllCorePpMon_t, PllCorePpMon_monPllCorePpPllLock_f, 0, &value, &core_pp_mon));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [DATAPATH] core %d pll pp cannot lock \n", core_id);
        return CTC_E_HW_NOT_LOCK;
    }
    CTC_ERROR_RETURN(_sys_at_datapath_read_core_table_field(lchip, core_id,
        PllTsMon_t, PllTsMon_monPllTsLock_f, 0, &value, &ts_mon));
    if(0 == value)
    {
        SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, " [DATAPATH] core %d pll ts cannot lock \n", core_id);
        return CTC_E_HW_NOT_LOCK;
    }
    return CTC_E_NONE;
}


STATIC int32
_sys_at_datapath_core_clock_init(uint8 lchip, uint16 core_pll_mhz)
{
#if (SDB_MEM_MODEL == SDB_MODE)
	return CTC_E_NONE;
#endif

#if !defined(EMULATION_ENV) && (SDK_WORK_PLATFORM == 0)
//#if (EMULATION_ENV == 0)
    uint8  core_id   = 0;
    uint8  core_num  = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;
    PllCoreDpCfg_m core_dp_cfg;
    PllCorePpCfg_m core_pp_cfg;
    PllTsCfg_m     ts_cfg;


    /* SupClockTreeCore PLL */
    for (core_id = 0; core_id < core_num; core_id++)
    {
        if (900 == core_pll_mhz)
        {
            /* DP Clock: 900M */
            CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                PllCoreDpCfg_t, PllCoreDpCfg_cfgPllCoreDpFbdivCenter_f, 0, 0x2D0000, &core_dp_cfg));
            CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                PllCoreDpCfg_t, PllCoreDpCfg_cfgPllCoreDpPostdivCh0_f,  0, 5, &core_dp_cfg));

            /* PP Clock: 1000M */
            CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                PllCorePpCfg_t, PllCorePpCfg_cfgPllCorePpFbdivCenter_f, 0, 0x320000, &core_pp_cfg));
            CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                PllCorePpCfg_t, PllCorePpCfg_cfgPllCorePpPostdivCh0_f,  0, 5, &core_pp_cfg));
            
        }
        else if (1350 == core_pll_mhz)
        {
            /* Default DP Clock: 1350M */
            CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                PllCoreDpCfg_t, PllCoreDpCfg_cfgPllCoreDpFbdivCenter_f, 0, 0x288000, &core_dp_cfg));
            CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                PllCoreDpCfg_t, PllCoreDpCfg_cfgPllCoreDpPostdivCh0_f,  0, 3, &core_dp_cfg));

            /* Default PP Clock: 1400M */
            CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                PllCorePpCfg_t, PllCorePpCfg_cfgPllCorePpFbdivCenter_f, 0, 0x2A0000, &core_pp_cfg));
            CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
                PllCorePpCfg_t, PllCorePpCfg_cfgPllCorePpPostdivCh0_f,  0, 3, &core_pp_cfg));
        }

        /* power up PLL */
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            PllCoreDpCfg_t, PllCoreDpCfg_cfgPllCoreDpPowerUp_f, 0, 1, &core_dp_cfg));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            PllCorePpCfg_t, PllCorePpCfg_cfgPllCorePpPowerUp_f, 0, 1, &core_pp_cfg));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            PllTsCfg_t, PllTsCfg_cfgPllTsPowerUp_f, 0, 1, &ts_cfg));

        sal_task_sleep(1);
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "delay 1\n");

        /* relase PLL reset */
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            PllCoreDpCfg_t, PllCoreDpCfg_cfgPllCoreDpReset_f, 0, 0, &core_dp_cfg));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            PllCorePpCfg_t, PllCorePpCfg_cfgPllCorePpReset_f, 0, 0, &core_pp_cfg));
        CTC_ERROR_RETURN(_sys_at_datapath_write_core_table_field(lchip, core_id,
            PllTsCfg_t, PllTsCfg_cfgPllTsReset_f, 0, 0, &ts_cfg));

        sal_task_sleep(1);
        SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "delay 1\n");

        /* check PLL lock */
        CTC_ERROR_RETURN(_sys_at_datapath_check_core_pll_lock(lchip, core_id));
    }

#endif

    CTC_ERROR_RETURN(sys_usw_dmps_db_set_core_pll(lchip, core_pll_mhz));

    return CTC_E_NONE;
}


#ifdef AT_SERDES_SIM
int32 sys_at_load_cpumachss_default_value(uint8 lchip)
{
    DP_DEBUG_FUNCTION_CALLED_PRINT();
    CpuMacHssTxCfg_m      CpuMacHssTxCfg        ;
    CpuMacHssTxTrainCfg_m CpuMacHssTxTrainCfg   ;
    CpuMacHssRxCfg_m      CpuMacHssRxCfg        ;
    CpuMacHssCmnCfg_m     CpuMacHssCmnCfg       ;
    CpuMacHssMon_m        CpuMacHssMon          ;
    CpuMacHssPramCfg_m    CpuMacHssPramCfg      ;
    CpuMacHssMcuCfg_m     CpuMacHssMcuCfg       ;
    CpuMacCtlEnClk_m      CpuMacCtlEnClk        ;
    CpuMacCtlResetCtl_m   CpuMacCtlResetCtl     ;
    CpuMacHssLaneCfg_m    CpuMacHssLaneCfg      ;
    
    uint32 index  = DRV_INS(0, 0);
    uint32 core   = 0;
    uint32 cmd    = 0;
    
    cmd = DRV_IOR(CpuMacHssTxCfg_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssTxCfg);
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "load CpuMacHssTxCfg\n");
    SetCpuMacHssTxCfg(V,cfgHssRefFrefSelTxLane2_f   	  ,&CpuMacHssTxCfg,7);
    SetCpuMacHssTxCfg(V,cfgHssRefFrefSelTxLane3_f         ,&CpuMacHssTxCfg,7);
    SetCpuMacHssTxCfg(V,cfgHssSscEnLane0_f                ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssSscEnLane1_f                ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssSscEnLane2_f                ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssSscEnLane3_f                ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxDclk4XEnLane0_f           ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxDclk4XEnLane1_f           ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxDclk4XEnLane2_f           ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxDclk4XEnLane3_f           ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxGrayCodeEnLane0_f         ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxGrayCodeEnLane1_f         ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxGrayCodeEnLane2_f         ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxGrayCodeEnLane3_f         ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxIdleLane0_f               ,&CpuMacHssTxCfg,1);
    SetCpuMacHssTxCfg(V,cfgHssTxIdleLane1_f               ,&CpuMacHssTxCfg,1);
    SetCpuMacHssTxCfg(V,cfgHssTxIdleLane2_f               ,&CpuMacHssTxCfg,1);
    SetCpuMacHssTxCfg(V,cfgHssTxIdleLane3_f               ,&CpuMacHssTxCfg,1);
    SetCpuMacHssTxCfg(V,cfgHssTxPreCodeEnLane0_f          ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxPreCodeEnLane1_f          ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxPreCodeEnLane2_f          ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxPreCodeEnLane3_f          ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssPmaTxClkDivEnLane0_f        ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssPmaTxClkDivEnLane1_f        ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssPmaTxClkDivEnLane2_f        ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssPmaTxClkDivEnLane3_f        ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssPmaTxClkDivSelLane2_f	      ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssPmaTxClkDivSelLane3_f       ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssRefFrefSelTxLane0_f         ,&CpuMacHssTxCfg,7);
    SetCpuMacHssTxCfg(V,cfgHssRefFrefSelTxLane1_f         ,&CpuMacHssTxCfg,7);
    SetCpuMacHssTxCfg(V,cfgHssTxDclk2XSelLane0_f          ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxDclk2XSelLane1_f          ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxDclk2XSelLane2_f          ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxDclk2XSelLane3_f          ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssPmaTxClkDivSelLane0_f       ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssPmaTxClkDivSelLane1_f       ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssRepeatModeEnLane0_f         ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssRepeatModeEnLane1_f         ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssRepeatModeEnLane2_f         ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssRepeatModeEnLane3_f         ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssRepeatTxClkFreqRatioLane0_f ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssRepeatTxClkFreqRatioLane1_f ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssRepeatTxClkFreqRatioLane2_f ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssRepeatTxClkFreqRatioLane3_f ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxAnethEnLane0_f            ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxAnethEnLane1_f            ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxAnethEnLane2_f            ,&CpuMacHssTxCfg,0);
    SetCpuMacHssTxCfg(V,cfgHssTxAnethEnLane3_f            ,&CpuMacHssTxCfg,0);
    cmd = DRV_IOW(CpuMacHssTxCfg_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssTxCfg);

    /*CpuMacHssTxTrainCfg */
    cmd = DRV_IOR(CpuMacHssTxTrainCfg_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssTxTrainCfg);
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "load CpuMacHssTxTrainCfg\n");
    SetCpuMacHssTxTrainCfg(V,cfgHssTxTrainEnableLane0_f     ,&CpuMacHssTxTrainCfg,0);
    SetCpuMacHssTxTrainCfg(V,cfgHssTxTrainEnableLane1_f     ,&CpuMacHssTxTrainCfg,0);
    SetCpuMacHssTxTrainCfg(V,cfgHssTxTrainEnableLane2_f     ,&CpuMacHssTxTrainCfg,0);
    SetCpuMacHssTxTrainCfg(V,cfgHssTxTrainEnableLane3_f     ,&CpuMacHssTxTrainCfg,0);
    SetCpuMacHssTxTrainCfg(V,cfgHssTxTrainEnableModeLane0_f ,&CpuMacHssTxTrainCfg,0);
    SetCpuMacHssTxTrainCfg(V,cfgHssTxTrainEnableModeLane1_f ,&CpuMacHssTxTrainCfg,0);
    SetCpuMacHssTxTrainCfg(V,cfgHssTxTrainEnableModeLane2_f ,&CpuMacHssTxTrainCfg,0);
    SetCpuMacHssTxTrainCfg(V,cfgHssTxTrainEnableModeLane3_f ,&CpuMacHssTxTrainCfg,0);
    cmd = DRV_IOW(CpuMacHssTxTrainCfg_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssTxTrainCfg);
    /*CpuMacHssMon*/
    cmd = DRV_IOR(CpuMacHssMon_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssMon);
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "load CpuMacHssMon\n");
    SetCpuMacHssMon(V,monHssCdrLockLane0_f         ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssCdrLockLane1_f         ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssCdrLockLane2_f         ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssCdrLockLane3_f         ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssPllReadyTxLane0_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssPllReadyTxLane1_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssPllReadyTxLane2_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssPllReadyTxLane3_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxDtlClampLane0_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxDtlClampLane1_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxDtlClampLane2_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxDtlClampLane3_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxInitDoneLane0_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxInitDoneLane1_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxInitDoneLane2_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxInitDoneLane3_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxRstAckLane0_f        ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxRstAckLane1_f        ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxRstAckLane2_f        ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxRstAckLane3_f        ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxSquelchDetLane0_f    ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxSquelchDetLane1_f    ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxSquelchDetLane2_f    ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxSquelchDetLane3_f    ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxSquelchDetLpfLane0_f ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxSquelchDetLpfLane1_f ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxSquelchDetLpfLane2_f ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxSquelchDetLpfLane3_f ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxRstAckLane0_f        ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxRstAckLane1_f        ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxRstAckLane2_f        ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxRstAckLane3_f        ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssPllReadyRxLane0_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssPllReadyRxLane1_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssPllReadyRxLane2_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssPllReadyRxLane3_f      ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxTrainCompleteLane0_f ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxTrainCompleteLane1_f ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxTrainCompleteLane2_f ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxTrainCompleteLane3_f ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxTrainFailedLane0_f   ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxTrainFailedLane1_f   ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxTrainFailedLane2_f   ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssRxTrainFailedLane3_f   ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxFloopClampLane0_f    ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxFloopClampLane1_f    ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxFloopClampLane2_f    ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxFloopClampLane3_f    ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxTrainCompleteLane0_f ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxTrainCompleteLane1_f ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxTrainCompleteLane2_f ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxTrainCompleteLane3_f ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxTrainErrorLane0_f    ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxTrainErrorLane1_f    ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxTrainErrorLane2_f    ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxTrainErrorLane3_f    ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxTrainFailedLane0_f   ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxTrainFailedLane1_f   ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxTrainFailedLane2_f   ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssTxTrainFailedLane3_f   ,&CpuMacHssMon,0);      
    SetCpuMacHssMon(V,monHssDigTestBus_f           ,&CpuMacHssMon,0);     
    cmd = DRV_IOW(CpuMacHssMon_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssMon);

    /*CpuMac Pram cfg*/
    cmd = DRV_IOR(CpuMacHssPramCfg_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssPramCfg);
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "load CpuMacHssPramCfg\n");
    SetCpuMacHssPramCfg(V,cfgPram1ErrReset_f    ,&CpuMacHssPramCfg, 0);       
    SetCpuMacHssPramCfg(V,cfgPram2ErrReset_f    ,&CpuMacHssPramCfg, 0);       
    SetCpuMacHssPramCfg(V,cfgPramBurstEn_f      ,&CpuMacHssPramCfg, 1);       
    SetCpuMacHssPramCfg(V,cfgPramChecksumEn_f   ,&CpuMacHssPramCfg, 0);       
    SetCpuMacHssPramCfg(V,cfgPramChecksumReset_f,&CpuMacHssPramCfg, 0);       
    SetCpuMacHssPramCfg(V,cfgPramChecksumSel_f  ,&CpuMacHssPramCfg, 0);       
    SetCpuMacHssPramCfg(V,cfgPramEccEn_f        ,&CpuMacHssPramCfg, 1);       
    SetCpuMacHssPramCfg(V,cfgPramInitEn_f       ,&CpuMacHssPramCfg, 0);       
    SetCpuMacHssPramCfg(V,cfgPramReset_f        ,&CpuMacHssPramCfg, 1);       
    SetCpuMacHssPramCfg(V,cfgPramSocEn_f        ,&CpuMacHssPramCfg, 1);       
    SetCpuMacHssPramCfg(V,cfgPramInitData_f     ,&CpuMacHssPramCfg, 0);      
    cmd = DRV_IOW(CpuMacHssPramCfg_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssPramCfg);

    /*CpuMacHssCmnCfg*/
    
    cmd = DRV_IOR(CpuMacHssCmnCfg_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssCmnCfg);
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "load CpuMacHssCmnCfg\n");
    SetCpuMacHssCmnCfg(V,cfgHssGenRxLane3_f        ,&CpuMacHssCmnCfg, 35 );  
    SetCpuMacHssCmnCfg(V,cfgHssGenTxLane3_f        ,&CpuMacHssCmnCfg, 35 );  
    SetCpuMacHssCmnCfg(V,cfgHssGenRxLane2_f        ,&CpuMacHssCmnCfg, 35 );  
    SetCpuMacHssCmnCfg(V,cfgHssGenTxLane2_f        ,&CpuMacHssCmnCfg, 35 );  
    SetCpuMacHssCmnCfg(V,cfgHssGenRxLane1_f        ,&CpuMacHssCmnCfg, 35 );  
    SetCpuMacHssCmnCfg(V,cfgHssGenTxLane1_f        ,&CpuMacHssCmnCfg, 35 );  
    SetCpuMacHssCmnCfg(V,cfgHssGenRxLane0_f        ,&CpuMacHssCmnCfg, 35 );  
    SetCpuMacHssCmnCfg(V,cfgHssGenTxLane0_f        ,&CpuMacHssCmnCfg, 35 );  
    SetCpuMacHssCmnCfg(V,cfgHssPhyMode_f           ,&CpuMacHssCmnCfg, 4  );   
    SetCpuMacHssCmnCfg(V,cfgHssPowerupIVref_f      ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssPowerupPllLane0_f   ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssPowerupPllLane1_f   ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssPowerupPllLane2_f   ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssPowerupPllLane3_f   ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssPowerupRxLane0_f    ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssPowerupRxLane1_f    ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssPowerupRxLane2_f    ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssPowerupRxLane3_f    ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssPowerupTxLane0_f    ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssPowerupTxLane1_f    ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssPowerupTxLane2_f    ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssPowerupTxLane3_f    ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssRefClkSelRxLane0_f  ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssRefClkSelRxLane1_f  ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssRefClkSelRxLane2_f  ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssRefClkSelRxLane3_f  ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssRefClkSelTxLane0_f  ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssRefClkSelTxLane1_f  ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssRefClkSelTxLane2_f  ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssRefClkSelTxLane3_f  ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssRxRstLane0_f        ,&CpuMacHssCmnCfg, 1  );   
    SetCpuMacHssCmnCfg(V,cfgHssRxRstLane1_f        ,&CpuMacHssCmnCfg, 1  );   
    SetCpuMacHssCmnCfg(V,cfgHssRxRstLane2_f        ,&CpuMacHssCmnCfg, 1  );   
    SetCpuMacHssCmnCfg(V,cfgHssRxRstLane3_f        ,&CpuMacHssCmnCfg, 1  );   
    SetCpuMacHssCmnCfg(V,cfgHssTxRstLane0_f        ,&CpuMacHssCmnCfg, 1  );   
    SetCpuMacHssCmnCfg(V,cfgHssTxRstLane1_f        ,&CpuMacHssCmnCfg, 1  );   
    SetCpuMacHssCmnCfg(V,cfgHssTxRstLane2_f        ,&CpuMacHssCmnCfg, 1  );   
    SetCpuMacHssCmnCfg(V,cfgHssTxRstLane3_f        ,&CpuMacHssCmnCfg, 1  );   
    SetCpuMacHssCmnCfg(V,cfgHssAvddSel_f           ,&CpuMacHssCmnCfg, 7  );   
    SetCpuMacHssCmnCfg(V,cfgHssCidRev_f            ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssCoupleModeEnLane0_f ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssCoupleModeEnLane1_f ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssCoupleModeEnLane2_f ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssCoupleModeEnLane3_f ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssDirectAccessEn_f    ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssFwReady_f           ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssGlobalRst_f         ,&CpuMacHssCmnCfg, 1  );   
    SetCpuMacHssCmnCfg(V,cfgHssPramSifSel_f        ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssSifSel_f            ,&CpuMacHssCmnCfg, 0  );   
    SetCpuMacHssCmnCfg(V,cfgHssSpeedCfg_f          ,&CpuMacHssCmnCfg, 2  );
    cmd = DRV_IOW(CpuMacHssCmnCfg_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssCmnCfg);

    /*CpuMacHssRxCfg*/
    cmd = DRV_IOR(CpuMacHssRxCfg_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssRxCfg);   
    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "load CpuMacHssRxCfg\n");
    SetCpuMacHssRxCfg(V,cfgHssRxDclk2XSelLane0_f   ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxDclk2XSelLane1_f   ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxDclk2XSelLane2_f   ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxDclk2XSelLane3_f   ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxDclk4XEnLane0_f    ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxDclk4XEnLane1_f    ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxDclk4XEnLane2_f    ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxDclk4XEnLane3_f    ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxDclkDivEnLane0_f   ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxDclkDivEnLane1_f   ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxDclkDivEnLane2_f   ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxDclkDivEnLane3_f   ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxDclkDivSelLane0_f  ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxDclkDivSelLane1_f  ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxDclkDivSelLane2_f  ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxDclkDivSelLane3_f  ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxInitLane0_f        ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxInitLane1_f        ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxInitLane2_f        ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxInitLane3_f        ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxTrainEnableLane0_f ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxTrainEnableLane1_f ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxTrainEnableLane2_f ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxTrainEnableLane3_f ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRefFrefSelRxLane0_f  ,&CpuMacHssRxCfg, 7);      
    SetCpuMacHssRxCfg(V,cfgHssRefFrefSelRxLane1_f  ,&CpuMacHssRxCfg, 7);      
    SetCpuMacHssRxCfg(V,cfgHssRefFrefSelRxLane2_f  ,&CpuMacHssRxCfg, 7);      
    SetCpuMacHssRxCfg(V,cfgHssRefFrefSelRxLane3_f  ,&CpuMacHssRxCfg, 7);      
    SetCpuMacHssRxCfg(V,cfgHssRxGrayCodeEnLane0_f  ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxGrayCodeEnLane1_f  ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxGrayCodeEnLane2_f  ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxGrayCodeEnLane3_f  ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxPreCodeEnLane0_f   ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxPreCodeEnLane1_f   ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxPreCodeEnLane2_f   ,&CpuMacHssRxCfg, 0);      
    SetCpuMacHssRxCfg(V,cfgHssRxPreCodeEnLane3_f   ,&CpuMacHssRxCfg, 0);
    cmd = DRV_IOW(CpuMacHssRxCfg_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssRxCfg);

    cmd = DRV_IOR(CpuMacHssMcuCfg_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssMcuCfg);

    SetCpuMacHssMcuCfg(V, cfgHssMcuFreq_f, &CpuMacHssMcuCfg, 0x180);
    
    cmd = DRV_IOW(CpuMacHssMcuCfg_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssMcuCfg);

    /*CpuMacCtlEnClk*/       
    cmd = DRV_IOR(CpuMacCtlEnClk_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacCtlEnClk);
    SetCpuMacCtlEnClk(V,enClkLed_f        , &CpuMacCtlEnClk, 1 ); 
    SetCpuMacCtlEnClk(V,enClkQuadSgmac_f  , &CpuMacCtlEnClk, 1 ); 
    SetCpuMacCtlEnClk(V,enClkSgmac0_f     , &CpuMacCtlEnClk, 1 ); 
    SetCpuMacCtlEnClk(V,enClkSgmac1_f     , &CpuMacCtlEnClk, 1 ); 
    SetCpuMacCtlEnClk(V,enClkSgmac2_f     , &CpuMacCtlEnClk, 1 ); 
    SetCpuMacCtlEnClk(V,enClkSgmac3_f     , &CpuMacCtlEnClk, 1 ); 
    SetCpuMacCtlEnClk(V,enClkSgmiiPcs0_f  , &CpuMacCtlEnClk, 1 ); 
    SetCpuMacCtlEnClk(V,enClkSgmiiPcs1_f  , &CpuMacCtlEnClk, 1 ); 
    SetCpuMacCtlEnClk(V,enClkSgmiiPcs2_f  , &CpuMacCtlEnClk, 1 ); 
    SetCpuMacCtlEnClk(V,enClkSgmiiPcs3_f  , &CpuMacCtlEnClk, 1 ); 
    SetCpuMacCtlEnClk(V,enClkXfiPcs0_f    , &CpuMacCtlEnClk, 1 ); 
    SetCpuMacCtlEnClk(V,enClkXfiPcs1_f    , &CpuMacCtlEnClk, 1 ); 
    SetCpuMacCtlEnClk(V,enClkXfiPcs2_f    , &CpuMacCtlEnClk, 1 ); 
    SetCpuMacCtlEnClk(V,enClkXfiPcs3_f    , &CpuMacCtlEnClk, 1 ); 
    cmd = DRV_IOW(CpuMacCtlEnClk_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacCtlEnClk);
    /*CpuMacCtlResetCtl*/    
    cmd = DRV_IOR(CpuMacCtlResetCtl_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacCtlResetCtl);
    SetCpuMacCtlResetCtl(V,resetCoreAnethLane0_f   , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreAnethLane1_f   , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreAnethLane2_f   , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreAnethLane3_f   , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreCgPcs_f        , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreCmn_f          , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreMii0_f         , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreMii1_f         , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreMii2_f         , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreMii3_f         , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCorePcs0_f         , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCorePcs1_f         , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCorePcs2_f         , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCorePcs3_f         , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreQuadSgmac_f    , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreSgmac0_f       , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreSgmac1_f       , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreSgmac2_f       , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreSgmac3_f       , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreSharedFecReg_f , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreSharedMiiReg_f , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreXlgPcs0_f      , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreXlgPcs1_f      , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetHssRxLane0_f       , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetHssRxLane1_f       , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetHssRxLane2_f       , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetHssRxLane3_f       , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetHssTxLane0_f       , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetHssTxLane1_f       , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetHssTxLane2_f       , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetHssTxLane3_f       , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetSharedFec_f        , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreAnethRegLane0_f, &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreAnethRegLane1_f, &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreAnethRegLane2_f, &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreAnethRegLane3_f, &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreQuadSgmacReg_f , &CpuMacCtlResetCtl, 1);      
    SetCpuMacCtlResetCtl(V,resetCoreSharedPcsReg_f , &CpuMacCtlResetCtl, 1); 
    cmd = DRV_IOW(CpuMacCtlResetCtl_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacCtlResetCtl);
    /*CpuMacHssLaneCfg*/     
    cmd = DRV_IOR(CpuMacHssLaneCfg_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssLaneCfg);
    SetCpuMacHssLaneCfg(V,cfgAnethTxReadyLane0_f              , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgAnethTxReadyLane1_f              , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgAnethTxReadyLane2_f              , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgAnethTxReadyLane3_f              , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4AnethEnLane0_f     , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4AnethEnLane1_f     , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4AnethEnLane2_f     , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4AnethEnLane3_f     , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4AnethValueLane0_f  , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4AnethValueLane1_f  , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4AnethValueLane2_f  , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4AnethValueLane3_f  , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4PcsEnLane0_f       , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4PcsEnLane1_f       , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4PcsEnLane2_f       , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4PcsEnLane3_f       , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4PcsValueLane0_f    , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4PcsValueLane1_f    , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4PcsValueLane2_f    , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgForcePmaReady4PcsValueLane3_f    , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgPmaReady4AnethMaskLane0_f        , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgPmaReady4AnethMaskLane1_f        , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgPmaReady4AnethMaskLane2_f        , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgPmaReady4AnethMaskLane3_f        , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgPmaReady4PcsMaskLane0_f          , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgPmaReady4PcsMaskLane1_f          , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgPmaReady4PcsMaskLane2_f          , &CpuMacHssLaneCfg, 0);
    SetCpuMacHssLaneCfg(V,cfgPmaReady4PcsMaskLane3_f          , &CpuMacHssLaneCfg, 0);
    cmd = DRV_IOW(CpuMacHssLaneCfg_t, DRV_ENTRY_FLAG);
    DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &CpuMacHssLaneCfg);

    DP_DEBUG_FUNCTION_RETURN_PRINT();
    return CTC_E_NONE;
}

int32 sys_at_datapath_init_serdes_temp(uint8 lchip, ctc_datapath_global_cfg_t* p_dp_cfg)
{
#ifdef AT_CPUMAC
    uint8 lane_idx = 0;
    uint16 lsd     = 0;
    uint8 mode     = 0;
#endif

    DP_DEBUG_FUNCTION_CALLED_PRINT();
#ifdef AT_CPUMAC
    for(lane_idx = 0; lane_idx < SYS_AT_CPUMAC_SERDES_NUM; lane_idx++)
    {
        lsd = DMPS_MAX_SERDES_NUM_PER_CORE * DMPS_MAX_CORE_NUM + lane_idx;
        mode = p_dp_cfg->serdes[lsd].mode;
        CTC_ERROR_RETURN(_sys_at_datapath_serdes_clktree_cpumac_cfg(lchip, lsd, mode));
    }
#endif    
    
    CTC_ERROR_RETURN(sys_at_serdes_init(lchip));

    DP_DEBUG_FUNCTION_RETURN_PRINT();
    
    return CTC_E_NONE;
}
#endif

int32 _sys_at_datapath_serdes_clktree_cpumac_cfg(uint8 lchip, uint16 lsd, uint8 mode)
{
    uint32 tbl_id;
    uint32 cmd;
    uint32 fld_id;
    uint32 index;
    uint32 core = 0;
    uint8  fld_idx;
    uint8  mode_idx;
    uint8  lane_id;
    uint8  fld_num;
    uint32 val_u32;

    sys_dmps_db_upt_info_t port_info;
    CpuMacClockTreeCfg_m clk_tree;

    uint32 clocktree_cfg[CpuMacClockTreeCfg_TOTALCNT][2] = {
        {CpuMacClockTreeCfg_cfgClockHss20Tx0Sel_f,        CpuMacClockTreeCfg_cfgClockHss20Tx1Sel_f      -  CpuMacClockTreeCfg_cfgClockHss20Tx0Sel_f},
        {CpuMacClockTreeCfg_cfgClockHssL0TxDiv2Sel_f,     CpuMacClockTreeCfg_cfgClockHssL1TxDiv2Sel_f   -  CpuMacClockTreeCfg_cfgClockHssL0TxDiv2Sel_f},
        {CpuMacClockTreeCfg_cfgClockHssL0TxL2Div2Sel_f,   CpuMacClockTreeCfg_cfgClockHssL1TxL2Div2Sel_f -  CpuMacClockTreeCfg_cfgClockHssL0TxL2Div2Sel_f},
        {CpuMacClockTreeCfg_cfgClockHssL0TxMultiLane_f,   CpuMacClockTreeCfg_cfgClockHssL1TxMultiLane_f -  CpuMacClockTreeCfg_cfgClockHssL0TxMultiLane_f},
        {CpuMacClockTreeCfg_cfgCwgph1HssL0TxDiv_f,        CpuMacClockTreeCfg_cfgCwgph1HssL1TxDiv_f      -  CpuMacClockTreeCfg_cfgCwgph1HssL0TxDiv_f},
        {CpuMacClockTreeCfg_cfgCwgph2HssL0TxDiv_f,        CpuMacClockTreeCfg_cfgCwgph2HssL1TxDiv_f      -  CpuMacClockTreeCfg_cfgCwgph2HssL0TxDiv_f},
        {CpuMacClockTreeCfg_cfgDivideHssL0TxDiv_f,        CpuMacClockTreeCfg_cfgDivideHssL1TxDiv_f      -  CpuMacClockTreeCfg_cfgDivideHssL0TxDiv_f},
        {CpuMacClockTreeCfg_cfgEdgeHssL0TxDiv_f,          CpuMacClockTreeCfg_cfgEdgeHssL1TxDiv_f        -  CpuMacClockTreeCfg_cfgEdgeHssL0TxDiv_f},
        {CpuMacClockTreeCfg_cfgExternalHssL0TxDiv_f,      CpuMacClockTreeCfg_cfgExternalHssL1TxDiv_f    -  CpuMacClockTreeCfg_cfgExternalHssL0TxDiv_f},
        {CpuMacClockTreeCfg_cfgHssL0Tx2RxLoopBackEn_f,    CpuMacClockTreeCfg_cfgHssL1Tx2RxLoopBackEn_f  -  CpuMacClockTreeCfg_cfgHssL0Tx2RxLoopBackEn_f},
        {CpuMacClockTreeCfg_cfgHssLane0And2SwapEn_f,      CpuMacClockTreeCfg_cfgHssLane0And2SwapEn_f    -  CpuMacClockTreeCfg_cfgHssLane0And2SwapEn_f},
        {CpuMacClockTreeCfg_cfgHssTxDataOutSelLane0_f,    CpuMacClockTreeCfg_cfgHssTxDataOutSelLane1_f  -  CpuMacClockTreeCfg_cfgHssTxDataOutSelLane0_f},
        {CpuMacClockTreeCfg_cfgInvertHssL0TxDiv_f,        CpuMacClockTreeCfg_cfgInvertHssL1TxDiv_f      -  CpuMacClockTreeCfg_cfgInvertHssL0TxDiv_f},
        {CpuMacClockTreeCfg_cfgLocalgoHssL0TxDiv_f,       CpuMacClockTreeCfg_cfgLocalgoHssL1TxDiv_f     -  CpuMacClockTreeCfg_cfgLocalgoHssL0TxDiv_f},
        {CpuMacClockTreeCfg_cfgResetHssL0TxDiv_f,         CpuMacClockTreeCfg_cfgResetHssL1TxDiv_f       -  CpuMacClockTreeCfg_cfgResetHssL0TxDiv_f},
        {CpuMacClockTreeCfg_cfgResetHssL0TxDiv2_f,        CpuMacClockTreeCfg_cfgResetHssL1TxDiv2_f      -  CpuMacClockTreeCfg_cfgResetHssL0TxDiv2_f},
        {CpuMacClockTreeCfg_cfgWidthHssL0TxDiv_f,         CpuMacClockTreeCfg_cfgWidthHssL1TxDiv_f       -  CpuMacClockTreeCfg_cfgWidthHssL0TxDiv_f}
    };

    uint32 value[CpuMacClockTreeCfg_TOTALCNT][AT_CPUMAC_SERDES_MAX_MODE] = 
    {   
        /* SGMII              2DOT5G                XFI                   XXVG    */
        {1,                    1,                    0,                    0},                    /*cfgClockHss20Tx0Sel*/
        {0,                    0,                    0,                    1},                    /*cfgClockHssL0TxDiv2Sel*/
        {0,                    0,                    0,                    0},                    /*cfgClockHssL0TxL2Div2Sel*/
        {0,                    0,                    0,                    0},                    /*cfgClockHssL0TxMultiLane*/
        {SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32},  /*cfgCwgph1HssL0TxDiv*/
        {SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32},  /*cfgCwgph2HssL0TxDiv*/
        {SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32,  1,                    1},                    /*cfgDivideHssL0TxDiv*/
        {SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32,  1,                    1},                    /*cfgEdgeHssL0TxDiv*/
        {0,                    0,                    0,                    0},                    /*cfgHssL0Tx2RxLoopBackEn*/
        {SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32},  /*cfgExternalHssL0TxDiv*/
        {0,                    0,                    0,                    0},                    /*cfgHssLane0And2SwapEn*/
        {0,                    0,                    2,                    3},                    /*cfgHssTxDataOutSelLane0*/
        {SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32,  0,                    0},                    /*cfgInvertHssL0TxDiv*/
        {SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32,  1,                    1},                    /*cfgLocalgoHssL0TxDiv*/
        {0,                    0,                    0,                    0},                    /*cfgResetHssL0TxDiv*/
        {SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32},  /*cfgResetHssL0TxDiv2*/
        {SYS_AT_USELESS_ID32,  SYS_AT_USELESS_ID32,  0,                    0},                    /*cfgWidthHssL0TxDiv*/
    };

    switch(mode)
    {
        case CTC_CHIP_SERDES_SGMII_MODE:
            mode_idx = AT_CPUMAC_SERDES_SGMII_MODE;
            break;
        case CTC_CHIP_SERDES_2DOT5G_MODE:
            mode_idx = AT_CPUMAC_SERDES_2DOT5G_MODE;
            break;
        case CTC_CHIP_SERDES_XFI_MODE:
            mode_idx = AT_CPUMAC_SERDES_XFI_MODE;
            break;
        case CTC_CHIP_SERDES_XXVG_MODE:
            mode_idx = AT_CPUMAC_SERDES_XXVG_MODE;
            break;
        case CTC_CHIP_SERDES_NONE_MODE:
        default:
            return CTC_E_NONE;
    }

    fld_num = sizeof(clocktree_cfg) / (sizeof(uint32) * 2);

    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "// Cpumac Clock tree cfg start, lsd %d\n", lsd);    
    CTC_ERROR_RETURN(sys_usw_dmps_db_upt_info_init(lchip, &port_info));
    DMPS_DB_SET_MAP_INFO(port_info, DMPS_DB_LOGIC_SERDES, lsd);
    DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, 0);
    DMPS_DB_SET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX, 0);
    CTC_ERROR_RETURN(sys_usw_dmps_db_get_port_info(lchip, &port_info));
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_CHAN_CORE_ID, core);
    DMPS_DB_GET_PROPERTY_INFO(port_info, DMPS_DB_PCS_IDX, lane_id);

    tbl_id = CpuMacClockTreeCfg_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG); 
    index = DRV_INS(0, 0);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &clk_tree));

    for(fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        if(value[fld_idx][mode_idx] == SYS_AT_USELESS_ID32)
        {
            continue;
        }
        fld_id = clocktree_cfg[fld_idx][0] + clocktree_cfg[fld_idx][1] * lane_id;
        DRV_IOW_FIELD_NZ(core, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &value[fld_idx][mode_idx], &clk_tree);
    }
    
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &clk_tree));

    /*do reset*/
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG); 
    index = DRV_INS(0, 0);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &clk_tree));

    val_u32 = 1;
    fld_id = clocktree_cfg[CpuMacClockTreeCfg_cfgResetHssL0TxDiv2][0] + lane_id * clocktree_cfg[CpuMacClockTreeCfg_cfgResetHssL0TxDiv2][1];
    DRV_IOW_FIELD_NZ(core, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &val_u32, &clk_tree);
    fld_id = clocktree_cfg[CpuMacClockTreeCfg_cfgResetHssL0TxDiv][0] + lane_id * clocktree_cfg[CpuMacClockTreeCfg_cfgResetHssL0TxDiv][1];
    DRV_IOW_FIELD_NZ(core, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &val_u32, &clk_tree);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &clk_tree));
    
    val_u32 = 0;
    fld_id = clocktree_cfg[CpuMacClockTreeCfg_cfgResetHssL0TxDiv2][0] + lane_id * clocktree_cfg[CpuMacClockTreeCfg_cfgResetHssL0TxDiv2][1];
    DRV_IOW_FIELD_NZ(core, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &val_u32, &clk_tree);
    fld_id = clocktree_cfg[CpuMacClockTreeCfg_cfgResetHssL0TxDiv][0] + lane_id * clocktree_cfg[CpuMacClockTreeCfg_cfgResetHssL0TxDiv][1];
    DRV_IOW_FIELD_NZ(core, 0xff, 0xff, lchip, tbl_id, 0, fld_id, &val_u32, &clk_tree);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core, cmd, &clk_tree));

    SYS_DMPS_DUMP_PRINT(g_tm_dump_fp, "// Cpumac Clock tree cfg end, lsd %d\n", lsd);    
    
    return CTC_E_NONE;
}

int32 
sys_at_datapath_init_get_hss_init_flag(uint8 lchip, uint8 core_id, ctc_datapath_global_cfg_t* p_dp_cfg, 
                                                   uint8 core_hss_flag[], uint8 psd_init_spd[])
{
    uint16 lsd;
    uint16 psd;
    uint16 lsd_nw_start  = (0 == core_id ? 0 : SYS_AT_NW_SERDES_NUM_PER_CORE);
    uint16 lsd_nw_end    = (0 == core_id ? SYS_AT_NW_SERDES_NUM_PER_CORE : SYS_AT_NW_SERDES_NUM);
    uint16 lsd_cpu_start = (0 == core_id ? AT_SERDES_CPUMAC_START_ID_CORE0 : AT_SERDES_CPUMAC_START_ID_CORE1);
    uint16 lsd_cpu_end   = (0 == core_id ? AT_SERDES_CPUMAC_START_ID_CORE1 : AT_SERDES_NUM_MAX);
    uint8  core_hss_id   = 0;
    uint8  spd_mode      = 0;
    uint16 mac_group_id  = 0;
    uint32 spd_value     = 0;

    /* NW */
    for(lsd = lsd_nw_start; lsd < lsd_nw_end; lsd++)
    {
        psd = p_dp_cfg->serdes[lsd].physical_serdes_id;
        SYS_CONDITION_CONTINUE((lsd_nw_start > psd) || (lsd_nw_end <= psd));
        mac_group_id = SYS_AT_GET_MAC_GROUP_BY_LSD_DC(lsd);
        SYS_CONDITION_CONTINUE(!SYS_AT_MAC_GROUP_IS_VAILD(lchip, core_id, mac_group_id));
        SYS_CONDITION_CONTINUE(SYS_AT_IS_SERDES_ABANDON(p_dp_cfg->serdes[lsd].mode, p_dp_cfg->serdes[lsd].is_dynamic));
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_serdes_speed(lchip, psd, &spd_value));
        SYS_USW_SERDES_VALUE_2_SPEED(spd_value, spd_mode);
        psd_init_spd[psd] = spd_mode;
        
        core_hss_id = SYS_AT_MAP_SERDES_TO_CORE_HSS(lsd);
        SYS_CONDITION_CONTINUE((AT_SERDES_CPUMAC_DPHSS <= core_hss_id) || (core_hss_flag[core_hss_id]));
        core_hss_flag[core_hss_id] = 1;
    }

    /* CpuMac */
    for(lsd = lsd_cpu_start; lsd < lsd_cpu_end; lsd++)
    {
        psd = p_dp_cfg->serdes[lsd].physical_serdes_id;
        if(psd != lsd) return CTC_E_INVALID_CONFIG;
        SYS_CONDITION_CONTINUE((lsd_cpu_start > psd) || (lsd_cpu_end <= psd));
        SYS_CONDITION_CONTINUE(SYS_AT_IS_SERDES_ABANDON(p_dp_cfg->serdes[lsd].mode, p_dp_cfg->serdes[lsd].is_dynamic));
        CTC_ERROR_RETURN(sys_usw_dmps_db_get_serdes_speed(lchip, psd, &spd_value));
        SYS_USW_SERDES_VALUE_2_SPEED(spd_value, spd_mode);
        psd_init_spd[psd] = spd_mode;
        
        core_hss_id = SYS_AT_MAP_SERDES_TO_CORE_HSS(lsd);
        SYS_CONDITION_CONTINUE((AT_SERDES_CPUMAC_DPHSS < core_hss_id) || (core_hss_flag[core_hss_id]));
        core_hss_flag[core_hss_id] = 1;
    }
    
    return CTC_E_NONE;
}

int32
sys_at_datapath_init_serdes(uint8 lchip, ctc_datapath_global_cfg_t* p_dp_cfg)
{
    uint8  core_num      = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;
    uint8  core_id       = 0;
    uint8  hss_core_id   = 0;
    uint16 psd           = 0;
    uint16 psd_nw_start  = 0;
    uint16 psd_nw_end    = 0;
    uint16 psd_cpu_start = 0;
    uint16 psd_cpu_end   = 0;
    uint16 mac_group_id  = 0;
    uint8  core_hss_flag[AT_SERDES_CPUMAC_DPHSS + 1] = {0};
    uint8  psd_init_spd[CTC_DATAPATH_SERDES_NUM]     = {0};

    for(core_id = 0; core_id < core_num; core_id++)
    {
        sal_memset(core_hss_flag, 0, (AT_SERDES_CPUMAC_DPHSS + 1) * sizeof(uint8));
        sal_memset(psd_init_spd,  0, CTC_DATAPATH_SERDES_NUM * sizeof(uint8));
        CTC_ERROR_RETURN(sys_at_datapath_init_get_hss_init_flag(lchip, core_id, p_dp_cfg, core_hss_flag, psd_init_spd));

        /*1. HSS power on, NW & CPUMAC*/
        for(hss_core_id = 0; hss_core_id <= AT_SERDES_CPUMAC_DPHSS; hss_core_id++)
        //for(hss_core_id = 0; hss_core_id < AT_SERDES_CPUMAC_DPHSS; hss_core_id++)/*BR_TODO*/
        {
            SYS_CONDITION_CONTINUE(0 == core_hss_flag[hss_core_id]);
            CTC_ERROR_RETURN(_sys_at_serdes_power_on_per_hss(lchip, core_id, hss_core_id));
        }
        /*2.1 LANE power on, NW*/
        psd_nw_start = (0 == core_id ? 0 : SYS_AT_NW_SERDES_NUM_PER_CORE);
        psd_nw_end = (0 == core_id ? SYS_AT_NW_SERDES_NUM_PER_CORE : SYS_AT_NW_SERDES_NUM);
        psd_cpu_start = (0 == core_id ? AT_SERDES_CPUMAC_START_ID_CORE0 : AT_SERDES_CPUMAC_START_ID_CORE1);
        psd_cpu_end = (0 == core_id ? AT_SERDES_CPUMAC_START_ID_CORE1 : AT_SERDES_NUM_MAX);
        for(psd = psd_nw_start; psd < psd_nw_end; psd++)
        {
            mac_group_id = SYS_AT_GET_MAC_GROUP_BY_LSD_DC(psd);
            SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PSD, psd));
            SYS_CONDITION_CONTINUE(!SYS_AT_MAC_GROUP_IS_VAILD(lchip, core_id, mac_group_id));
            CTC_ERROR_RETURN(_sys_at_serdes_lane_power_on_pre_cfg(lchip, psd));
            SYS_CONDITION_CONTINUE(SERDES_SPEED_0G == psd_init_spd[psd]);
            CTC_ERROR_RETURN(_sys_at_serdes_lane_power_on_cfg(lchip, psd, psd_init_spd[psd]));
        }
        for(psd = psd_cpu_start; psd < psd_cpu_end; psd++)
        {
            SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PSD, psd));
            CTC_ERROR_RETURN(_sys_at_datapath_serdes_clktree_cpumac_cfg(lchip, psd, p_dp_cfg->serdes[psd].mode));
            CTC_ERROR_RETURN(_sys_at_serdes_lane_power_on_pre_cfg(lchip, psd));
            SYS_CONDITION_CONTINUE(SERDES_SPEED_0G == psd_init_spd[psd]);
            CTC_ERROR_RETURN(_sys_at_serdes_lane_power_on_cfg(lchip, psd, psd_init_spd[psd]));
        }
        for(psd = psd_nw_start; psd < psd_nw_end; psd++)
        {
            SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PSD, psd));
            mac_group_id = SYS_AT_GET_MAC_GROUP_BY_LSD_DC(psd);
            SYS_CONDITION_CONTINUE(!SYS_AT_MAC_GROUP_IS_VAILD(lchip, core_id, mac_group_id));
            SYS_CONDITION_CONTINUE(SERDES_SPEED_0G == psd_init_spd[psd]);
            CTC_ERROR_RETURN(_sys_at_serdes_lane_power_on_post_cfg(lchip, psd, psd_init_spd[psd]));
        }
        for(psd = psd_cpu_start; psd < psd_cpu_end; psd++)
        {
            SYS_CONDITION_CONTINUE(FALSE == sys_usw_dmps_db_is_valid_id(lchip, DMPS_DB_TYPE_PSD, psd));
            SYS_CONDITION_CONTINUE(SERDES_SPEED_0G == psd_init_spd[psd]);
            CTC_ERROR_RETURN(_sys_at_serdes_lane_power_on_post_cfg(lchip, psd, psd_init_spd[psd]));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_init_mux_agg(uint8 lchip)
{
    uint8  core_num = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;
    uint8  core_id = 0;
    uint32 cmd     = 0;
    uint32 tbl_id  = 0;
    uint32 index   = 0;
    uint32 value   = 0;
    SupSelMacAgg_m    mac_agg;
    SupTxqmMuxCtl_m   txqm_mux;
    SupSliceSwapCtl_m slice_swap;
    PGMiscCfg_m       pg_misc_cfg;

    if (DRV_CHIP_SUB_TYPE_1 == SYS_AT_GET_CHIP_TYPE(lchip))
    {
        if (AT_CHIP_IS_SERDES_AG_LOW(lchip))
        {
            /* If all serdes are used when chip_type is 9260, mux agg should be reconfig */
            tbl_id = PGMiscCfg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgSliceMaskVec_f,  &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgRemoteMaskVec_f, &value, &pg_misc_cfg);
            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));

            value = 0xffff;
            cmd   = DRV_IOW(PGRlmSlice0ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));
            cmd   = DRV_IOW(PGRlmSlice1ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));
            cmd   = DRV_IOW(PGRlmSlice2ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));
            cmd   = DRV_IOW(PGRlmSlice3ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));

            tbl_id = PGMiscCfg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgCpuMacPortSwap_f,  &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgOamSliceSel_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccGetTableSliceSel_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingGetTableSliceSel_f, &value, &pg_misc_cfg);
            value = 0xe4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cpuMapLogicSliceIdBmp_f, &value, &pg_misc_cfg);
            value = 0xfac688;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStoreLogicSliceIdBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStorePhySliceIdBmpProcTop_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStorePhySliceIdBmpSliceQuad_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrEnqLogicSliceIdBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrEnqPhySliceIdBmp_f, &value, &pg_misc_cfg);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStoreLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStoreRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrDeqLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrDeqRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_metFifoSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_postBrLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_preBrLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_postBrRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_preBrRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_linkAggSliceFailBmp_f, &value, &pg_misc_cfg);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice0Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice0Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice1Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice1Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice2Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice2Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice3Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice3Enable_f, &value, &pg_misc_cfg);
            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));

            /* mac_agg */
            tbl_id = SupSelMacAgg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_agg));

            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx0_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx0_f, &value, &mac_agg);
            value = 2;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx1_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx1_f, &value, &mac_agg);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx2_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx2_f, &value, &mac_agg);
            value = 2;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx3_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx3_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx4_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx4_f, &value, &mac_agg);
            value = 5;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx5_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx5_f, &value, &mac_agg);
            value = 5;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx6_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx6_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx7_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx7_f, &value, &mac_agg);
            value = 2;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx8_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx8_f, &value, &mac_agg);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx9_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx9_f, &value, &mac_agg);
            value = 2;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx10_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx10_f, &value, &mac_agg);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx11_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx11_f, &value, &mac_agg);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_agg));

            /* txqm mux */
            tbl_id = SupTxqmMuxCtl_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &txqm_mux));

            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx0_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx0_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx1_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx1_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx2_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx2_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx3_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx3_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx4_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx4_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx5_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx5_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx6_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx6_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx7_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx7_f, &value, &txqm_mux);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &txqm_mux));
        }
        else if (AT_CHIP_IS_SERDES_AG_HIGH(lchip))
        {
            tbl_id = SupSelMacAgg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_agg));

            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx0_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx0_f, &value, &mac_agg);
            value = 3;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx1_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx1_f, &value, &mac_agg);
            value = 3;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx2_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx2_f, &value, &mac_agg);
            value = 2;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx3_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx3_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx4_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx4_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx5_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx5_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx6_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx6_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx7_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx7_f, &value, &mac_agg);
            value = 2;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx8_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx8_f, &value, &mac_agg);
            value = 3;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx9_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx9_f, &value, &mac_agg);
            value = 3;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx10_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx10_f, &value, &mac_agg);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx11_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx11_f, &value, &mac_agg);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_agg));

            /* txqm mux */
            tbl_id = SupTxqmMuxCtl_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &txqm_mux));

            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx0_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx0_f, &value, &txqm_mux);
            value = 2;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx1_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx1_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx2_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx2_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx3_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx3_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx4_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx4_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx5_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx5_f, &value, &txqm_mux);
            value = 2;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx6_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx6_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx7_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx7_f, &value, &txqm_mux);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &txqm_mux));
        }
        else if (AT_CHIP_IS_SERDES_PG_HIGH(lchip))
        {
            tbl_id = PGMiscCfg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgSliceMaskVec_f,  &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgRemoteMaskVec_f, &value, &pg_misc_cfg);
            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));

            value = 0xffff;
            cmd   = DRV_IOW(PGRlmSlice0ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));
            cmd   = DRV_IOW(PGRlmSlice1ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));
            cmd   = DRV_IOW(PGRlmSlice2ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));
            cmd   = DRV_IOW(PGRlmSlice3ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));

            tbl_id = PGMiscCfg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgCpuMacPortSwap_f,  &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgOamSliceSel_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccGetTableSliceSel_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingGetTableSliceSel_f, &value, &pg_misc_cfg);
            value = 0xe4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cpuMapLogicSliceIdBmp_f, &value, &pg_misc_cfg);
            value = 0xfac688;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStoreLogicSliceIdBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStorePhySliceIdBmpProcTop_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStorePhySliceIdBmpSliceQuad_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrEnqLogicSliceIdBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrEnqPhySliceIdBmp_f, &value, &pg_misc_cfg);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStoreLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStoreRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrDeqLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrDeqRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_metFifoSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_postBrLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_preBrLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_postBrRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_preBrRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_linkAggSliceFailBmp_f, &value, &pg_misc_cfg);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice0Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice0Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice1Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice1Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice2Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice2Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice3Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice3Enable_f, &value, &pg_misc_cfg);
            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));

            tbl_id = SupSelMacAgg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_agg));

            value = 6;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx0_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx0_f, &value, &mac_agg);
            value = 6;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx1_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx1_f, &value, &mac_agg);
            value = 3;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx2_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx2_f, &value, &mac_agg);
            value = 2;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx3_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx3_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx4_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx4_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx5_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx5_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx6_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx6_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx7_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx7_f, &value, &mac_agg);
            value = 2;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx8_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx8_f, &value, &mac_agg);
            value = 3;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx9_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx9_f, &value, &mac_agg);
            value = 6;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx10_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx10_f, &value, &mac_agg);
            value = 6;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx11_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx11_f, &value, &mac_agg);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_agg));

            /* txqm mux */
            tbl_id = SupTxqmMuxCtl_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &txqm_mux));

            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx0_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx0_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx1_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx1_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx2_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx2_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx3_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx3_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx4_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx4_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx5_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx5_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx6_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx6_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx7_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx7_f, &value, &txqm_mux);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &txqm_mux));
        }
        else if (AT_CHIP_IS_SERDES_PG_LOW(lchip))
        {
            tbl_id = PGMiscCfg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));
            value = 8;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgSliceMaskVec_f,  &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgRemoteMaskVec_f, &value, &pg_misc_cfg);
            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));

            value = 0xffff;
            cmd   = DRV_IOW(PGRlmSlice0ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));
            cmd   = DRV_IOW(PGRlmSlice1ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));
            cmd   = DRV_IOW(PGRlmSlice2ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));
            value = 0;
            cmd   = DRV_IOW(PGRlmSlice3ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));

            tbl_id = PGMiscCfg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgCpuMacPortSwap_f,  &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgOamSliceSel_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice3Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice3Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccGetTableSliceSel_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingGetTableSliceSel_f, &value, &pg_misc_cfg);
            value = 0xe4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cpuMapLogicSliceIdBmp_f, &value, &pg_misc_cfg);
            value = 0x1ac088;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStoreLogicSliceIdBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStorePhySliceIdBmpProcTop_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStorePhySliceIdBmpSliceQuad_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrEnqLogicSliceIdBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrEnqPhySliceIdBmp_f, &value, &pg_misc_cfg);
            value = 8;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStoreLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStoreRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrDeqLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrDeqRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_metFifoSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_postBrLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_preBrLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_postBrRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_preBrRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_linkAggSliceFailBmp_f, &value, &pg_misc_cfg);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice0Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice0Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice1Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice1Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice2Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice2Enable_f, &value, &pg_misc_cfg);
            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));

            tbl_id = SupSelMacAgg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_agg));

            value = 6;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx0_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx0_f, &value, &mac_agg);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx1_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx1_f, &value, &mac_agg);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx2_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx2_f, &value, &mac_agg);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx3_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx3_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx4_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx4_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx5_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx5_f, &value, &mac_agg);
            value = 5;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx6_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx6_f, &value, &mac_agg);
            value = 5;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx7_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx7_f, &value, &mac_agg);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx8_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx8_f, &value, &mac_agg);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx9_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx9_f, &value, &mac_agg);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx10_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx10_f, &value, &mac_agg);
            value = 7;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx11_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx11_f, &value, &mac_agg);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_agg));

            /* txqm mux */
            tbl_id = SupTxqmMuxCtl_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &txqm_mux));

            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx0_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx0_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx1_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx1_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx2_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx2_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx3_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx3_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx4_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx4_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx5_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx5_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx6_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx6_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx7_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx7_f, &value, &txqm_mux);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &txqm_mux));

            /* SupSliceSwapCtl */
            tbl_id = SupSliceSwapCtl_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &slice_swap));

            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx0_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx1_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx2_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx3_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx4_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx5_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx6_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx7_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx0_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx1_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx2_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx3_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx4_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx5_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx6_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx7_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx0_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx1_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx2_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx3_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx4_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx5_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx6_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx7_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx0_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx1_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx2_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx3_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx4_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx5_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx6_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx7_f, &value, &slice_swap);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &slice_swap));
        }
    }
    else if (AT_CHIP_IS_SERDES_DCM_PG_LOW(lchip))
    {
        for (core_id = 0; core_id < core_num; core_id++)
        {
            tbl_id = PGMiscCfg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));
            value = 8;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgSliceMaskVec_f,  &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgRemoteMaskVec_f, &value, &pg_misc_cfg);
            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));

            value = 0xffff;
            cmd   = DRV_IOW(PGRlmSlice0ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));
            cmd   = DRV_IOW(PGRlmSlice1ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));
            cmd   = DRV_IOW(PGRlmSlice2ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));
            value = 0;
            cmd   = DRV_IOW(PGRlmSlice3ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));

            tbl_id = PGMiscCfg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgCpuMacPortSwap_f,  &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgOamSliceSel_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice3Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice3Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccGetTableSliceSel_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingGetTableSliceSel_f, &value, &pg_misc_cfg);
            value = 0xe4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cpuMapLogicSliceIdBmp_f, &value, &pg_misc_cfg);
            value = 0x1ac088;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStoreLogicSliceIdBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStorePhySliceIdBmpProcTop_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStorePhySliceIdBmpSliceQuad_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrEnqLogicSliceIdBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrEnqPhySliceIdBmp_f, &value, &pg_misc_cfg);
            value = 8;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStoreLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStoreRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrDeqLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrDeqRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_metFifoSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_postBrLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_preBrLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_postBrRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_preBrRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_linkAggSliceFailBmp_f, &value, &pg_misc_cfg);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice0Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice0Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice1Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice1Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice2Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice2Enable_f, &value, &pg_misc_cfg);
            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));

            tbl_id = SupSelMacAgg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_agg));

            value = 6;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx0_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx0_f, &value, &mac_agg);
            value = 6;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx1_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx1_f, &value, &mac_agg);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx2_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx2_f, &value, &mac_agg);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx3_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx3_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx4_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx4_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx5_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx5_f, &value, &mac_agg);
            value = 5;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx6_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx6_f, &value, &mac_agg);
            value = 5;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx7_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx7_f, &value, &mac_agg);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx8_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx8_f, &value, &mac_agg);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx9_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx9_f, &value, &mac_agg);
            value = 7;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx10_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx10_f, &value, &mac_agg);
            value = 7;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx11_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx11_f, &value, &mac_agg);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_agg));

            /* txqm mux */
            tbl_id = SupTxqmMuxCtl_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &txqm_mux));

            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx0_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx0_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx1_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx1_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx2_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx2_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx3_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx3_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx4_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx4_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx5_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx5_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx6_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx6_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx7_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx7_f, &value, &txqm_mux);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &txqm_mux));

            /* SupSliceSwapCtl */
            tbl_id = SupSliceSwapCtl_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &slice_swap));

            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx0_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx1_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx2_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx3_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx4_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx5_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx6_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx7_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx0_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx1_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx2_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx3_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx4_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx5_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx6_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx7_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx0_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx1_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx2_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx3_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx4_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx5_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx6_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx7_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx0_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx1_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx2_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx3_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx4_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx5_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx6_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx7_f, &value, &slice_swap);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &slice_swap));
        }
    }
    else if (DRV_CHIP_SUB_TYPE_3 == SYS_AT_GET_CHIP_TYPE(lchip))
    {
        for (core_id = 0; core_id < SYS_AT_CORE_NUM; core_id++)
        {
            tbl_id = PGMiscCfg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgSliceMaskVec_f,  &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgRemoteMaskVec_f, &value, &pg_misc_cfg);
            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));

            value = 0xffff;
            cmd   = DRV_IOW(PGRlmSlice0ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));
            cmd   = DRV_IOW(PGRlmSlice1ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));
            cmd   = DRV_IOW(PGRlmSlice2ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));
            cmd   = DRV_IOW(PGRlmSlice3ClkEnable_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &value));

            tbl_id = PGMiscCfg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgCpuMacPortSwap_f,  &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgOamSliceSel_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccGetTableSliceSel_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingGetTableSliceSel_f, &value, &pg_misc_cfg);
            value = 0xe4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cpuMapLogicSliceIdBmp_f, &value, &pg_misc_cfg);
            value = 0xfac688;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStoreLogicSliceIdBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStorePhySliceIdBmpProcTop_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStorePhySliceIdBmpSliceQuad_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrEnqLogicSliceIdBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrEnqPhySliceIdBmp_f, &value, &pg_misc_cfg);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStoreLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_bufStoreRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrDeqLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_qMgrDeqRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_metFifoSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_postBrLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_preBrLocalSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_postBrRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_preBrRemoteSliceFailBmp_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_linkAggSliceFailBmp_f, &value, &pg_misc_cfg);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice0Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice0Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice1Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice1Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice2Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice2Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgFibAccSetTableSlice3Enable_f, &value, &pg_misc_cfg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, PGMiscCfg_cfgPpAgingSetTableSlice3Enable_f, &value, &pg_misc_cfg);
            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &pg_misc_cfg));

            tbl_id = SupSelMacAgg_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_agg));

            value = 6;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx0_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx0_f, &value, &mac_agg);
            value = 6;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx1_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx1_f, &value, &mac_agg);
            value = 3;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx2_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx2_f, &value, &mac_agg);
            value = 2;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx3_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx3_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx4_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx4_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx5_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx5_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx6_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx6_f, &value, &mac_agg);
            value = 4;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx7_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx7_f, &value, &mac_agg);
            value = 2;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx8_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx8_f, &value, &mac_agg);
            value = 3;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx9_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx9_f, &value, &mac_agg);
            value = 6;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx10_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx10_f, &value, &mac_agg);
            value = 6;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggRx11_f, &value, &mac_agg);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSelMacAgg_cfgSelMacAggTx11_f, &value, &mac_agg);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &mac_agg));

            /* txqm mux */
            tbl_id = SupTxqmMuxCtl_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &txqm_mux));

            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx0_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx0_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx1_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx1_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx2_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx2_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx3_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx3_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx4_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx4_f, &value, &txqm_mux);
            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx5_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx5_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx6_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx6_f, &value, &txqm_mux);
            value = 1;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxRx7_f, &value, &txqm_mux);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupTxqmMuxCtl_cfgSelTxqmMuxTx7_f, &value, &txqm_mux);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &txqm_mux));

            /* SupSliceSwapCtl */
            tbl_id = SupSliceSwapCtl_t;
            cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &slice_swap));

            value = 0;
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx0_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx1_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx2_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx3_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx4_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx5_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx6_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxRx7_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx0_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx1_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx2_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx3_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx4_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx5_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx6_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapDpMuxTx7_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx0_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx1_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx2_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx3_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx4_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx5_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx6_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxRx7_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx0_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx1_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx2_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx3_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx4_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx5_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx6_f, &value, &slice_swap);
            DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, index, SupSliceSwapCtl_cfgSwapTxqmMuxTx7_f, &value, &slice_swap);

            cmd   = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &slice_swap));
        }
    }

    return CTC_E_NONE;
}

int32
_sys_at_datapath_init_buf_size(uint8 lchip, ctc_datapath_global_cfg_t* p_dp_cfg)
{
    uint8  core_id  = 0;
    uint8  core_num = 0;
    uint32 cmd      = 0;
    uint32 value1   = 0;
    uint32 value2   = 0;
    uint32 value3   = 0;
    uint32 value4   = 0;
    uint32 value5   = 0;
    uint32 value6   = 0;
    BufStoreUcFreePtrCtl_m bs_uc_free_ctl;
    BufStoreMcFreePtrCtl_m bs_mc_free_ctl;
    BufRetrvMcBufCfg_m     bs_retrv_mc_buf_cfg;

    core_num = (SYS_AT_CHIP_IS_DC(lchip)) ? 2 : 1;

    switch(p_dp_cfg->buffer_size)
    {
    case 8:
        value1 = 4;
        value2 = 124;
        value3 = 15;
        value4 = 16;
        value5 = 128;
        value6 = 8;
        break;
    case 16:
        value1 = 8;
        value2 = 120;
        value3 = 31;
        value4 = 32;
        value5 = 256;
        value6 = 16;
        break;
    case 48:
        value1 = 24;
        value2 = 104;
        value3 = 95;
        value4 = 96;
        value5 = 768;
        value6 = 48;
        break;
    default: /*32K*/
        value1 = 16;
        value2 = 112;
        value3 = 63;
        value4 = 64;
        value5 = 512;
        value6 = 32;
        break;
    }

    for (core_id = 0; core_id < core_num; core_id++)
    {
        cmd    = DRV_IOR(BufStoreUcFreePtrCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &bs_uc_free_ctl));
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, BufStoreUcFreePtrCtl_t, 0,
            BufStoreUcFreePtrCtl_freePtrRamAddrStart_f, &value1, &bs_uc_free_ctl);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, BufStoreUcFreePtrCtl_t, 0,
            BufStoreUcFreePtrCtl_cfgFreePtrRamAddrCnt_f, &value2, &bs_uc_free_ctl);
        cmd    = DRV_IOW(BufStoreUcFreePtrCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &bs_uc_free_ctl));

        cmd    = DRV_IOR(BufStoreMcFreePtrCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &bs_mc_free_ctl));
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, BufStoreMcFreePtrCtl_t, 0,
            BufStoreMcFreePtrCtl_freePtrRamAddrEnd_f, &value3, &bs_mc_free_ctl);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, BufStoreUcFreePtrCtl_t, 0,
            BufStoreMcFreePtrCtl_cfgFreePtrRamAddrCnt_f, &value4, &bs_mc_free_ctl);
        cmd    = DRV_IOW(BufStoreMcFreePtrCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &bs_mc_free_ctl));

        cmd    = DRV_IOR(BufRetrvMcBufCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &bs_retrv_mc_buf_cfg));
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, BufRetrvMcBufCfg_t, 0,
            BufRetrvMcBufCfg_maxMcPtrCfg_f, &value5, &bs_retrv_mc_buf_cfg);
        cmd    = DRV_IOW(BufRetrvMcBufCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, 0, core_id, cmd, &bs_retrv_mc_buf_cfg));
    }

    MCHIP_CAP(SYS_CAP_QOS_DROP_TOTAL_NON_UC_POOL_SIZE) = value6 * 1024;
    MCHIP_CAP(SYS_CAP_QOS_DROP_TOTAL_UC_POOL_SIZE)     = MCHIP_CAP(SYS_CAP_QOS_DROP_TOTAL_POOL_SIZE) - value6 * 1024;

    return CTC_E_NONE;
}

extern int32
_sys_usw_dmps_db_dump(uint8 lchip, uint8 db_type, sal_file_t fp);

/*extern ctc_vti_t* g_ctc_vti;*/
int32
sys_at_datapath_init(uint8 lchip, ctc_datapath_global_cfg_t* p_dp_cfg)
{
    if (NULL == p_dp_cfg)
    {
        return CTC_E_INVALID_PARAM;
    }
//#if (SDK_WORK_PLATFORM == 1)  || defined(EMULATION_ENV)
    if(g_dmps_dbg_sw)
    {
        if(NULL == g_tm_dump_fp)
        {
            g_tm_dump_fp = sal_fopen("./dump.txt", "w+");
        }
    }
    /*datapath_print(lchip, p_dp_cfg);*/
    /*p_dp_cfg->bpe_full_mode = 1;*/

    DP_DEBUG_FUNCTION_CALLED_PRINT();

    CTC_ERROR_RETURN(sys_at_datapath_init_db(lchip, p_dp_cfg));

    /* If all serdes are used when chip_type is scm ag, mux agg should be reinit */
    CTC_ERROR_RETURN(_sys_at_datapath_init_mux_agg(lchip));

    /*do core clock init*/
    CTC_ERROR_RETURN(_sys_at_datapath_core_clock_init(lchip, p_dp_cfg->core_frequency_a));

#if defined(EMULATION_ENV) && (PCS_ONLY == 0)
    extern ctc_cmd_element_t cli_com_source_file_cmd;
    extern int cli_com_source_file(ctc_cmd_element_t *, ctc_vti_t *, int, char **);
    uint8 chip_type    = SYS_AT_GET_CHIP_TYPE(lchip);
    char str[256] = "";
    char* argv[2];

/* partialgoodcfg.tcl */
#ifdef EMULATOR_ENV
    sal_printf("chip type is %d \n", chip_type);
    sal_strcpy(str, "/asiclab/asic/arcticemul/asic/20220119_emulator_fchip_init/partialgoodcfg_1pp.tcl");
    sal_printf("/asiclab/asic/arcticemul/asic/20220119_emulator_fchip_init/partialgoodcfg_1pp.tcl\n");
    argv[0] = str;
    cli_com_source_file(&cli_com_source_file_cmd, g_ctc_vti, 1, argv);

    sal_strcpy(str, "/asiclab/asic/arcticemul/dmps/miaoy/AT/emulator_load_macagg_cfg");
    sal_printf("/asiclab/asic/arcticemul/dmps/miaoy/AT/emulator_load_macagg_cfg\n");
    argv[0] = str;
    cli_com_source_file(&cli_com_source_file_cmd, g_ctc_vti, 1, argv);
#else
    switch (chip_type)
    {
        case DRV_CHIP_SUB_TYPE_2:
            sal_strcpy(str, "/systest/asiclab/data/asic/arcticemul/asic/20220119_pp_fchip_init/partialgoodcfg_pp0.tcl");
            sal_printf("/systest/asiclab/data/asic/arcticemul/asic/20220119_pp_fchip_init/partialgoodcfg_pp0.tcl\n");
            argv[0] = str;
            cli_com_source_file(&cli_com_source_file_cmd, g_ctc_vti, 1, argv);

            sal_strcpy(str, "/systest/asiclab/data/miaoy/AT/Emu/mux_pg.tcl");
            sal_printf("/systest/asiclab/data/miaoy/AT/Emu/mux_pg.tcl\n");
            argv[0] = str;
            cli_com_source_file(&cli_com_source_file_cmd, g_ctc_vti, 1, argv);
            break;
        case DRV_CHIP_SUB_TYPE_1:
            if (AT_CHIP_IS_SERDES_AG(lchip))
            {
                sal_strcpy(str, "/systest/asiclab/data/asic/arcticemul/asic/20220119_pp_fchip_init/partialgoodcfg.tcl");
                sal_printf("/systest/asiclab/data/asic/arcticemul/asic/20220119_pp_fchip_init/partialgoodcfg.tcl\n");
                argv[0] = str;
                cli_com_source_file(&cli_com_source_file_cmd, g_ctc_vti, 1, argv);

                sal_strcpy(str, "/systest/asiclab/data/miaoy/AT/Emu/mux_m60.tcl");
                sal_printf("/systest/asiclab/data/miaoy/AT/Emu/mux_m60.tcl\n");
                argv[0] = str;
                cli_com_source_file(&cli_com_source_file_cmd, g_ctc_vti, 1, argv);
            }
            break;
        case SYS_AT_SUBTYPE_1PP:
            sal_strcpy(str, "/systest/asiclab/data/miaoy/AT/Emu/1pp_cfg/paritial_All_good_1pp0.tcl");
            sal_printf("/systest/asiclab/data/miaoy/AT/Emu/1pp_cfg/paritial_All_good_1pp0.tcl\n");
            argv[0] = str;
            cli_com_source_file(&cli_com_source_file_cmd, g_ctc_vti, 1, argv);
            break;
        default:
            break;
    }
#endif
#endif

#ifdef AT_SERDES_SIM
    (void)sys_at_load_cpumachss_default_value(lchip);
#endif

    /*do sup init*/
    CTC_ERROR_RETURN(_sys_at_datapath_init_sup(lchip));

    /*set mc buffer size*/
    CTC_ERROR_RETURN(_sys_at_datapath_init_buf_size(lchip, p_dp_cfg));

    /*module init*/
    CTC_ERROR_RETURN(_sys_at_datapath_init_module(lchip));

    /*power down*/
    CTC_ERROR_RETURN(_sys_at_datapath_power_down_dp(lchip));

    /*manual_patch*/
#if defined(EMULATION_ENV) && (PCS_ONLY == 0)
#ifdef EMULATOR_ENV
    /* Emulator */
    CTC_ERROR_RETURN(_sys_at_datapath_init_manual_patch(lchip));
#else
    /* 1PP/2PP Emulation */
    if (DRV_CHIP_SUB_TYPE_1 == chip_type)
    {
        /* config when partial good */
        sal_strcpy(str, "/systest/asiclab/data/asic/arcticemul/asic/20220119_pp_fchip_init/pg_manual_patch.tcl");
        sal_printf("/systest/asiclab/data/asic/arcticemul/asic/20220119_pp_fchip_init/pg_manual_patch.tcl\n");
        argv[0] = str;
        cli_com_source_file(&cli_com_source_file_cmd, g_ctc_vti, 1, argv);
    }
    else
    {
        CTC_ERROR_RETURN(_sys_at_datapath_init_manual_patch(lchip));
    }
#endif
#else
    /* PCS_ONLY/UML/DEMO */
    CTC_ERROR_RETURN(_sys_at_datapath_init_manual_patch(lchip));
#endif

    /*do datapath init */
    CTC_ERROR_RETURN(_sys_at_datapath_init_dp(lchip, p_dp_cfg));

#if defined(EMULATION_ENV) && (PCS_ONLY == 0)
#ifdef EMULATOR_ENV
    sal_strcpy(str, "/asiclab/asic/arcticemul/asic/emulator_fchip_init/core2_qmgr_flush.tcl");
    sal_printf("/asiclab/asic/arcticemul/asic/emulator_fchip_init/core2_qmgr_flush.tcl\n");
    argv[0] = str;
    cli_com_source_file(&cli_com_source_file_cmd, g_ctc_vti, 1, argv);

    sal_strcpy(str, "/asiclab/asic/arcticemul/asic/datapath_init/Mrm.tcl");
    sal_printf("/asiclab/asic/arcticemul/asic/datapath_init/Mrm.tcl\n");
    argv[0] = str;
    cli_com_source_file(&cli_com_source_file_cmd, g_ctc_vti, 1, argv);

    sal_strcpy(str, "/asiclab/asic/arcticemul/asic/emulator_fchip_init/core2_FaultFilterEn.tcl");
    sal_printf("/asiclab/asic/arcticemul/asic/emulator_fchip_init/core2_FaultFilterEn.tcl\n");
    argv[0] = str;
    cli_com_source_file(&cli_com_source_file_cmd, g_ctc_vti, 1, argv);
#else
    if (SYS_AT_SUBTYPE_1PP == chip_type)
    {
        sal_strcpy(str, "/systest/asiclab/data/miaoy/AT/Emu/1pp_cfg/qmgr_flush.tcl");
        sal_printf("/systest/asiclab/data/miaoy/AT/Emu/1pp_cfg/qmgr_flush.tcl\n");
        argv[0] = str;
        cli_com_source_file(&cli_com_source_file_cmd, g_ctc_vti, 1, argv);
    }
    else
    {
        sal_strcpy(str, "/systest/asiclab/data/asic/arcticemul/asic/20220119_pp_fchip_init/qmgr_flush.tcl");
        sal_printf("/systest/asiclab/data/asic/arcticemul/asic/20220119_pp_fchip_init/qmgr_flush.tcl\n");
        argv[0] = str;
        cli_com_source_file(&cli_com_source_file_cmd, g_ctc_vti, 1, argv);
    }
#endif
#endif

    /*pulse init*/
    CTC_ERROR_RETURN(_sys_at_datapath_init_pulse(lchip));

    /* mcu init */
    CTC_ERROR_RETURN(sys_at_mcu_init(lchip));

#if !defined(EMULATION_ENV) && (SDK_WORK_PLATFORM == 0)
    CTC_ERROR_RETURN(sys_at_datapath_init_serdes(lchip, p_dp_cfg));
#endif

#ifdef AT_SERDES_SIM
    CTC_ERROR_RETURN(sys_at_datapath_init_serdes_temp(lchip, p_dp_cfg));
#endif
    DP_DEBUG_FUNCTION_RETURN_PRINT();

    return CTC_E_NONE;
}

#endif
